tu: support KHR_8bit_storage
Add basic KHR_8bit_storage support for Adreno 750 devices, for now enabling the storageBuffer8BitAccess feature. A separate descriptor is provided for 8-bit storage access. The descriptor index is adjusted appropriately for 8-bit SSBO loads and stores. The 8-bit SSBO loads cannot go through isam since that instruction isn't able to handle those. The ldib and stib instruction encodings are a bit peculiar but they match the blob's image buffer access through VK_FORMAT_R8 and the dedicated descriptor. These loads and stores do not work in vectorized form, so they have to be scalarized. Additionally stores of 8-bit values have to clear up higher bits of those values. 8-bit truncation can leave higher bits as undefined. Zero-extension of 8-bit values has to use masking since the corresponding cov instruction doesn't function as intended. 8-bit sign extension through cov from a non-shared to a shared register also doesn't work, so an exception is applied to avoid it. Conversion of 8-bit values to and from floating-point values also doesn't work with a straightforward cov instruction, instead the conversion has to go through a 16-bit value. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9979 Signed-off-by: Zan Dobersek <zdobersek@igalia.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28254>
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@@ -448,7 +448,7 @@ Vulkan 1.1 -- all DONE: anv, lvp, nvk, radv, tu, vn
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Vulkan 1.2 -- all DONE: anv, nvk, tu, vn
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VK_KHR_8bit_storage DONE (anv, dzn, hasvk, lvp, nvk, radv, v3dv, vn)
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VK_KHR_8bit_storage DONE (anv, dzn, hasvk, lvp, nvk, radv, tu/a750+, v3dv, vn)
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VK_KHR_buffer_device_address DONE (anv, hasvk, lvp, nvk, panvk, radv, tu, v3dv, vn)
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VK_KHR_create_renderpass2 DONE (anv, dzn, hasvk, lvp, nvk, radv, tu, v3dv, vn)
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VK_KHR_depth_stencil_resolve DONE (anv, dzn, hasvk, lvp, nvk, radv, tu, v3dv, vn)
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