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radeonsi: enable vrs2x2 coarse shading if flat shading (v9)

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Enable vrs2x2 coarse shading if flat shading as per
idea and guidance given by Marek.

is_flat_shading variable in struct si_shader_info is set
based on the data from gather_intrinsic_info() function
and struct si_state_rasterizer. If is_flat_shading_variable
is set, then in function si_emit_db_render_state() vrs2x2
shading is enabled in hardware.

v2: Fix review comments from Pierre-Eric. Code optimizations.
v3: Fix indentation style issue.
v4: Fix review comments from Marek. Fixed logical issue pointed
    by Marek where info->is_flat_shading variable can be corrupted
    and other code cleanup.
v5: Make the code compact as suggested by Pierre-Eric.
v6: Fix new review comments from Marek.
v7: use info->uses_interp_color variable fix from Marek.
v8: Fix coding style comment from Marek.
v9: Add uses_fbfetch_output check as suggested by Marek.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8161>
This commit is contained in:
Yogesh mohan marimuthu
2020-12-14 21:26:27 +05:30
parent 40a554c8dd
commit 8a22fc9502
5 changed files with 60 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/gallium/drivers/radeonsi/si_pipe.h
View File

@@ -1125,6 +1125,7 @@ struct si_context {
bool db_stencil_disable_expclear : 1;
bool occlusion_queries_disabled : 1;
bool generate_mipmap_for_depth : 1;
bool allow_flat_shading : 1;
/* Emitted draw state. */
bool gs_tri_strip_adj_fix : 1;

5
src/gallium/drivers/radeonsi/si_shader.h
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@@ -397,6 +397,11 @@ struct si_shader_info {
/** Whether all codepaths write tess factors in all invocations. */
bool tessfactors_are_def_in_all_invocs;
/* A flag to check if vrs2x2 can be enabled to reduce number of
* fragment shader invocations if flat shading.
*/
bool allow_flat_shading;
};
/* A shader selector is a gallium CSO and contains shader variants and

16
src/gallium/drivers/radeonsi/si_shader_nir.c
View File

@@ -427,6 +427,22 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
scan_instruction(nir, info, instr);
}
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
info->allow_flat_shading = !(info->uses_persp_center || info->uses_persp_centroid ||
info->uses_persp_sample || info->uses_linear_center ||
info->uses_linear_centroid || info->uses_linear_sample ||
info->uses_interp_at_sample || nir->info.writes_memory ||
nir->info.fs.uses_fbfetch_output ||
nir->info.fs.needs_quad_helper_invocations ||
(nir->info.system_values_read &
(BITFIELD64_BIT(SYSTEM_VALUE_FRAG_COORD) |
BITFIELD64_BIT(SYSTEM_VALUE_POINT_COORD) |
BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_ID) |
BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_POS) |
BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_MASK_IN) |
BITFIELD64_BIT(SYSTEM_VALUE_HELPER_INVOCATION))));
}
/* Add color inputs to the list of inputs. */
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
for (unsigned i = 0; i < 2; i++) {

36
src/gallium/drivers/radeonsi/si_state.c
View File

@@ -1412,19 +1412,29 @@ static void si_emit_db_render_state(struct si_context *sctx)
radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
db_shader_control);
if (sctx->screen->options.vrs2x2) {
/* If the shader is using discard, turn off coarse shading because
* discard at 2x2 pixel granularity degrades quality too much.
*
* MIN allows sample shading but not coarse shading.
*/
unsigned mode = G_02880C_KILL_ENABLE(db_shader_control) ? V_028064_VRS_COMB_MODE_MIN
: V_028064_VRS_COMB_MODE_PASSTHRU;
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_VRS_OVERRIDE_CNTL,
S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
S_028064_VRS_OVERRIDE_RATE_X(0) |
S_028064_VRS_OVERRIDE_RATE_Y(0));
if (sctx->chip_class >= GFX10_3) {
if (sctx->allow_flat_shading) {
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_VRS_OVERRIDE_CNTL,
S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(
V_028064_VRS_COMB_MODE_OVERRIDE) |
S_028064_VRS_OVERRIDE_RATE_X(1) |
S_028064_VRS_OVERRIDE_RATE_Y(1));
} else {
/* If the shader is using discard, turn off coarse shading because
* discard at 2x2 pixel granularity degrades quality too much.
*
* MIN allows sample shading but not coarse shading.
*/
unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU;
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_VRS_OVERRIDE_CNTL,
S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
S_028064_VRS_OVERRIDE_RATE_X(0) |
S_028064_VRS_OVERRIDE_RATE_Y(0));
}
}
if (initial_cdw != sctx->gfx_cs.current.cdw)

15
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@@ -4105,6 +4105,21 @@ bool si_update_shaders(struct si_context *sctx)
if (sctx->framebuffer.nr_samples <= 1)
si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
}
if (sctx->chip_class >= GFX10_3) {
struct si_shader_info *info = &sctx->ps_shader.cso->info;
bool allow_flat_shading = info->allow_flat_shading;
if (allow_flat_shading &&
(rs->line_smooth || rs->poly_smooth || rs->poly_stipple_enable ||
(!rs->flatshade && info->uses_interp_color)))
allow_flat_shading = false;
if (sctx->allow_flat_shading != allow_flat_shading) {
sctx->allow_flat_shading = allow_flat_shading;
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
}
}
}
if (si_pm4_state_enabled_and_changed(sctx, ls) || si_pm4_state_enabled_and_changed(sctx, hs) ||