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intel/fs/xe2+: Update BS payload setup for Xe2 reg size.

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Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Caio Oliveira
2022-09-11 00:57:26 -07:00
committed by Jordan Justen
parent 14e1b9ee69
commit 8944ac7d6c
3 changed files with 12 additions and 7 deletions
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2
src/intel/compiler/brw_fs.cpp
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@@ -7368,7 +7368,7 @@ fs_visitor::run_bs(bool allow_spilling)
{
assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
payload_ = new bs_thread_payload();
payload_ = new bs_thread_payload(*this);
emit_nir_code();

2
src/intel/compiler/brw_fs.h
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@@ -167,7 +167,7 @@ struct task_mesh_thread_payload : public cs_thread_payload {
};
struct bs_thread_payload : public thread_payload {
bs_thread_payload();
bs_thread_payload(const fs_visitor &v);
fs_reg global_arg_ptr;
fs_reg local_arg_ptr;

15
src/intel/compiler/brw_fs_thread_payload.cpp
View File

@@ -468,17 +468,22 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v)
num_regs = r;
}
bs_thread_payload::bs_thread_payload()
bs_thread_payload::bs_thread_payload(const fs_visitor &v)
{
unsigned r = 0;
/* R0: Thread header. */
r += reg_unit(v.devinfo);
/* R1: Stack IDs. */
r += reg_unit(v.devinfo);
/* R2: Argument addresses. */
global_arg_ptr = brw_ud1_grf(2, 0);
local_arg_ptr = brw_ud1_grf(2, 2);
/* R2: Inline Parameter. Used for argument addresses. */
global_arg_ptr = brw_ud1_grf(r, 0);
local_arg_ptr = brw_ud1_grf(r, 2);
r += reg_unit(v.devinfo);
num_regs = 3;
num_regs = r;
}
void