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intel/dev: Add gtt_size to devinfo

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13647>
This commit is contained in:
Jason Ekstrand
2021-11-03 08:59:53 -05:00
committed by Marge Bot
parent 1f559930b6
commit 88e97d75d0
7 changed files with 29 additions and 63 deletions
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20
src/gallium/drivers/iris/iris_bufmgr.c
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@@ -2121,21 +2121,6 @@ iris_reg_read(struct iris_bufmgr *bufmgr, uint32_t offset, uint64_t *result)
return ret;
}
static uint64_t
iris_gtt_size(int fd)
{
/* We use the default (already allocated) context to determine
* the default configuration of the virtual address space.
*/
struct drm_i915_gem_context_param p = {
.param = I915_CONTEXT_PARAM_GTT_SIZE,
};
if (!intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &p))
return p.value;
return 0;
}
static struct intel_buffer *
intel_aux_map_buffer_alloc(void *driver_ctx, uint32_t size)
{
@@ -2232,8 +2217,7 @@ iris_bufmgr_query_meminfo(struct iris_bufmgr *bufmgr)
static struct iris_bufmgr *
iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
{
uint64_t gtt_size = iris_gtt_size(fd);
if (gtt_size <= IRIS_MEMZONE_OTHER_START)
if (devinfo->gtt_size <= IRIS_MEMZONE_OTHER_START)
return NULL;
struct iris_bufmgr *bufmgr = calloc(1, sizeof(*bufmgr));
@@ -2298,7 +2282,7 @@ iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
*/
util_vma_heap_init(&bufmgr->vma_allocator[IRIS_MEMZONE_OTHER],
IRIS_MEMZONE_OTHER_START,
(gtt_size - _4GB) - IRIS_MEMZONE_OTHER_START);
(devinfo->gtt_size - _4GB) - IRIS_MEMZONE_OTHER_START);
init_cache_buckets(bufmgr, false);
init_cache_buckets(bufmgr, true);

17
src/intel/dev/intel_device_info.c
View File

@@ -1224,6 +1224,22 @@ getparam(int fd, uint32_t param, int *value)
return true;
}
static bool
get_context_param(int fd, uint32_t context, uint32_t param, uint64_t *value)
{
struct drm_i915_gem_context_param gp = {
.ctx_id = context,
.param = param,
};
int ret = intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &gp);
if (ret != 0)
return false;
*value = gp.value;
return true;
}
static void
update_cs_workgroup_threads(struct intel_device_info *devinfo)
{
@@ -1701,6 +1717,7 @@ intel_get_device_info_from_fd(int fd, struct intel_device_info *devinfo)
devinfo->has_bit6_swizzle = devinfo->ver < 8 && has_bit6_swizzle(fd);
intel_get_aperture_size(fd, &devinfo->aperture_bytes);
get_context_param(fd, 0, I915_CONTEXT_PARAM_GTT_SIZE, &devinfo->gtt_size);
devinfo->has_tiling_uapi = has_get_tiling(fd);
devinfo->subslice_total = 0;

1
src/intel/dev/intel_device_info.h
View File

@@ -347,6 +347,7 @@ struct intel_device_info
uint64_t timestamp_frequency;
uint64_t aperture_bytes;
uint64_t gtt_size;
/**
* ID to put into the .aub files.

30
src/intel/vulkan/anv_device.c
View File

@@ -437,27 +437,6 @@ anv_update_meminfo(struct anv_physical_device *device, int fd)
static VkResult
anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
{
if (anv_gem_get_context_param(fd, 0, I915_CONTEXT_PARAM_GTT_SIZE,
&device->gtt_size) == -1) {
/* If, for whatever reason, we can't actually get the GTT size from the
* kernel (too old?) fall back to the aperture size.
*/
anv_perf_warn(VK_LOG_NO_OBJS(&device->instance->vk),
"Failed to get I915_CONTEXT_PARAM_GTT_SIZE: %m");
if (device->info.aperture_bytes == 0) {
return vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
"failed to get aperture size: %m");
}
device->gtt_size = device->info.aperture_bytes;
}
/* We only allow 48-bit addresses with softpin because knowing the actual
* address is required for the vertex cache flush workaround.
*/
device->supports_48bit_addresses = (device->info.ver >= 8) &&
device->gtt_size > (4ULL << 30 /* GiB */);
VkResult result = anv_init_meminfo(device, fd);
if (result != VK_SUCCESS)
return result;
@@ -889,6 +868,15 @@ anv_physical_device_try_create(struct anv_instance *instance,
device->max_context_priority = priorities[i];
}
device->gtt_size = device->info.gtt_size ? device->info.gtt_size :
device->info.aperture_bytes;
/* We only allow 48-bit addresses with softpin because knowing the actual
* address is required for the vertex cache flush workaround.
*/
device->supports_48bit_addresses = (device->info.ver >= 8) &&
device->gtt_size > (4ULL << 30 /* GiB */);
/* Initialize memory regions struct to 0. */
memset(&device->vram, 0, sizeof(device->vram));
memset(&device->sys, 0, sizeof(device->sys));

16
src/intel/vulkan/anv_gem.c
View File

@@ -362,22 +362,6 @@ anv_gem_set_context_param(int fd, int context, uint32_t param, uint64_t value)
return err;
}
int
anv_gem_get_context_param(int fd, int context, uint32_t param, uint64_t *value)
{
struct drm_i915_gem_context_param gp = {
.ctx_id = context,
.param = param,
};
int ret = intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &gp);
if (ret == -1)
return -1;
*value = gp.value;
return 0;
}
int
anv_gem_context_get_reset_stats(int fd, int context,
uint32_t *active, uint32_t *pending)

6
src/intel/vulkan/anv_gem_stubs.c
View File

@@ -155,12 +155,6 @@ anv_gem_set_context_param(int fd, int context, uint32_t param, uint64_t value)
unreachable("Unused");
}
int
anv_gem_get_context_param(int fd, int context, uint32_t param, uint64_t *value)
{
unreachable("Unused");
}
bool
anv_gem_has_context_priority(int fd, int priority)
{

2
src/intel/vulkan/anv_private.h
View File

@@ -1369,8 +1369,6 @@ bool anv_gem_has_context_priority(int fd, int priority);
int anv_gem_destroy_context(struct anv_device *device, int context);
int anv_gem_set_context_param(int fd, int context, uint32_t param,
uint64_t value);
int anv_gem_get_context_param(int fd, int context, uint32_t param,
uint64_t *value);
int anv_gem_get_param(int fd, uint32_t param);
int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
int anv_gem_context_get_reset_stats(int fd, int context,