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radv: export SampleMask from pixel shaders at full rate

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Use 16_ABGR instead of 32_ABGR if Z isn't written.

Ported from RadeonSI.

No CTS regressions on Polaris.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2017-12-14 13:51:47 +01:00
parent 45872a0a6d
commit 88522e2bcd
2 changed files with 41 additions and 16 deletions
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46
src/amd/common/ac_nir_to_llvm.c
View File

@@ -32,6 +32,7 @@
#include <llvm-c/Transforms/Scalar.h> #include <llvm-c/Transforms/Scalar.h>
#include "ac_shader_abi.h" #include "ac_shader_abi.h"
#include "ac_shader_info.h" #include "ac_shader_info.h"
#include "ac_shader_util.h"
#include "ac_exp_param.h" #include "ac_exp_param.h"
enum radeon_llvm_calling_convention { enum radeon_llvm_calling_convention {
@@ -6211,19 +6212,42 @@ si_export_mrt_z(struct nir_to_llvm_context *ctx,
args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */ args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */ args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
if (depth) { unsigned format = ac_get_spi_shader_z_format(depth != NULL,
args.out[0] = depth; stencil != NULL,
args.enabled_channels |= 0x1; samplemask != NULL);
}
if (stencil) { if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
args.out[1] = stencil; assert(!depth);
args.enabled_channels |= 0x2; args.compr = 1; /* COMPR flag */
}
if (samplemask) { if (stencil) {
args.out[2] = samplemask; /* Stencil should be in X[23:16]. */
args.enabled_channels |= 0x4; stencil = ac_to_integer(&ctx->ac, stencil);
stencil = LLVMBuildShl(ctx->builder, stencil,
LLVMConstInt(ctx->ac.i32, 16, 0), "");
args.out[0] = ac_to_float(&ctx->ac, stencil);
args.enabled_channels |= 0x3;
}
if (samplemask) {
/* SampleMask should be in Y[15:0]. */
args.out[1] = samplemask;
args.enabled_channels |= 0xc;
}
} else {
if (depth) {
args.out[0] = depth;
args.enabled_channels |= 0x1;
}
if (stencil) {
args.out[1] = stencil;
args.enabled_channels |= 0x2;
}
if (samplemask) {
args.out[2] = samplemask;
args.enabled_channels |= 0x4;
}
} }
/* SI (except OLAND and HAINAN) has a bug that it only looks /* SI (except OLAND and HAINAN) has a bug that it only looks

11
src/amd/vulkan/radv_pipeline.c
View File

@@ -46,6 +46,7 @@
#include "vk_format.h" #include "vk_format.h"
#include "util/debug.h" #include "util/debug.h"
#include "ac_exp_param.h" #include "ac_exp_param.h"
#include "ac_shader_util.h"
static void static void
radv_pipeline_destroy(struct radv_device *device, radv_pipeline_destroy(struct radv_device *device,
@@ -2108,11 +2109,11 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
if (pipeline->device->physical_device->has_rbplus) if (pipeline->device->physical_device->has_rbplus)
pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1); pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
pipeline->graphics.shader_z_format = unsigned shader_z_format =
ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR : ac_get_spi_shader_z_format(ps->info.fs.writes_z,
ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR : ps->info.fs.writes_stencil,
ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R : ps->info.fs.writes_sample_mask);
V_028710_SPI_SHADER_ZERO; pipeline->graphics.shader_z_format = shader_z_format;
calculate_vgt_gs_mode(pipeline); calculate_vgt_gs_mode(pipeline);
calculate_vs_outinfo(pipeline); calculate_vs_outinfo(pipeline);