radv: export SampleMask from pixel shaders at full rate

Use 16_ABGR instead of 32_ABGR if Z isn't written.

Ported from RadeonSI.

No CTS regressions on Polaris.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2017-12-14 13:51:47 +01:00
parent 45872a0a6d
commit 88522e2bcd
2 changed files with 41 additions and 16 deletions

View File

@@ -46,6 +46,7 @@
#include "vk_format.h"
#include "util/debug.h"
#include "ac_exp_param.h"
#include "ac_shader_util.h"
static void
radv_pipeline_destroy(struct radv_device *device,
@@ -2108,11 +2109,11 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
if (pipeline->device->physical_device->has_rbplus)
pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
pipeline->graphics.shader_z_format =
ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
V_028710_SPI_SHADER_ZERO;
unsigned shader_z_format =
ac_get_spi_shader_z_format(ps->info.fs.writes_z,
ps->info.fs.writes_stencil,
ps->info.fs.writes_sample_mask);
pipeline->graphics.shader_z_format = shader_z_format;
calculate_vgt_gs_mode(pipeline);
calculate_vs_outinfo(pipeline);