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broadcom/compiler: add FLAFIRST and FLNAFIRST opcodes

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We will at least need the former to implement subgroupElect()

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>
This commit is contained in:
Iago Toral Quiroga
2021-06-23 11:18:50 +02:00
parent a9ad04f17d
commit 87fa5908b3
4 changed files with 13 additions and 1 deletions
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2
src/broadcom/compiler/v3d_compiler.h
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@@ -1234,6 +1234,8 @@ VIR_A_ALU1(NEG)
VIR_A_ALU1(FLAPUSH)
VIR_A_ALU1(FLBPUSH)
VIR_A_ALU1(FLPOP)
VIR_A_ALU0(FLAFIRST)
VIR_A_ALU0(FLNAFIRST)
VIR_A_ALU1(SETMSF)
VIR_A_ALU1(SETREVF)
VIR_A_ALU0(TIDX)

6
src/broadcom/qpu/qpu_instr.c
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@@ -137,6 +137,8 @@ v3d_qpu_add_op_name(enum v3d_qpu_add_op op)
[V3D_QPU_A_TMUWT] = "tmuwt",
[V3D_QPU_A_VPMSETUP] = "vpmsetup",
[V3D_QPU_A_VPMWT] = "vpmwt",
[V3D_QPU_A_FLAFIRST] = "flafirst",
[V3D_QPU_A_FLNAFIRST] = "flnafirst",
[V3D_QPU_A_LDVPMV_IN] = "ldvpmv_in",
[V3D_QPU_A_LDVPMV_OUT] = "ldvpmv_out",
[V3D_QPU_A_LDVPMD_IN] = "ldvpmd_in",
@@ -406,6 +408,8 @@ static const uint8_t add_op_args[] = {
[V3D_QPU_A_BARRIERID] = D,
[V3D_QPU_A_TMUWT] = D,
[V3D_QPU_A_VPMWT] = D,
[V3D_QPU_A_FLAFIRST] = D,
[V3D_QPU_A_FLNAFIRST] = D,
[V3D_QPU_A_VPMSETUP] = D | A,
@@ -930,6 +934,8 @@ v3d_qpu_reads_flags(const struct v3d_qpu_instr *inst)
case V3D_QPU_A_VFLNB:
case V3D_QPU_A_FLAPUSH:
case V3D_QPU_A_FLBPUSH:
case V3D_QPU_A_FLAFIRST:
case V3D_QPU_A_FLNAFIRST:
return true;
default:
break;

2
src/broadcom/qpu/qpu_instr.h
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@@ -191,6 +191,8 @@ enum v3d_qpu_add_op {
V3D_QPU_A_TMUWT,
V3D_QPU_A_VPMSETUP,
V3D_QPU_A_VPMWT,
V3D_QPU_A_FLAFIRST,
V3D_QPU_A_FLNAFIRST,
V3D_QPU_A_LDVPMV_IN,
V3D_QPU_A_LDVPMV_OUT,
V3D_QPU_A_LDVPMD_IN,

4
src/broadcom/qpu/qpu_pack.c
View File

@@ -519,8 +519,10 @@ static const struct opcode_desc add_ops[] = {
{ 187, 187, 1 << 2, 1 << 4, V3D_QPU_A_BARRIERID, 40 },
{ 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
{ 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT },
{ 187, 187, 1 << 2, 1 << 7, V3D_QPU_A_FLAFIRST, 41 },
{ 187, 187, 1 << 3, 1 << 0, V3D_QPU_A_FLNAFIRST, 41 },
{ 187, 187, 1 << 3, ANYMUX, V3D_QPU_A_VPMSETUP, 33 },
{ 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_IN, 40 },
{ 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_OUT, 40 },
{ 188, 188, 1 << 1, ANYMUX, V3D_QPU_A_LDVPMD_IN, 40 },