From 87bfad9efae485e6cc714c1a47d856f17d088beb Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 12 Apr 2024 15:48:56 +0200 Subject: [PATCH] etnaviv: rs: treat depth-only clear to X8Z24 surfaces as full clear X8Z24 surfaces have a don't care stencil channel, which is okay to be cleared together with the depth channel. Set the depth clear bits accordingly to allow those clears to use the fast-clear path when only depth is to be cleared. This change aligns the RS with the BLT ZS clear path. Fixes: df63f188e83a ("etnaviv: fix separate depth/stencil clears") Signed-off-by: Lucas Stach Reviewed-by: Christian Gmeiner Part-of: --- src/gallium/drivers/etnaviv/etnaviv_rs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.c b/src/gallium/drivers/etnaviv/etnaviv_rs.c index fc0880ef40a..97d6b99adf6 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_rs.c +++ b/src/gallium/drivers/etnaviv/etnaviv_rs.c @@ -380,10 +380,10 @@ etna_blit_clear_zs_rs(struct pipe_context *pctx, struct pipe_surface *dst, /* Get the channels to clear */ switch (surf->base.format) { case PIPE_FORMAT_Z16_UNORM: + case PIPE_FORMAT_X8Z24_UNORM: clear_bits_depth = 0xffff; clear_bits_stencil = 0; break; - case PIPE_FORMAT_X8Z24_UNORM: case PIPE_FORMAT_S8_UINT_Z24_UNORM: clear_bits_depth = 0xeeee; clear_bits_stencil = 0x1111;