radv: replace blend_enable_4bit by radv_pipeline_is_blend_enabled()

Same logic, though this workaround shouldn't be determined from the
pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>
This commit is contained in:
Samuel Pitoiset
2023-01-04 14:42:25 +01:00
committed by Marge Bot
parent 0768cc5ed1
commit 87b88de973

View File

@@ -51,8 +51,6 @@
#include "vk_format.h" #include "vk_format.h"
struct radv_blend_state { struct radv_blend_state {
uint32_t blend_enable_4bit;
uint32_t spi_shader_col_format; uint32_t spi_shader_col_format;
uint32_t cb_shader_mask; uint32_t cb_shader_mask;
}; };
@@ -689,8 +687,6 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline,
blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(gfx_level, dstA)); blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(gfx_level, dstA));
} }
pipeline->cb_blend_control[i] = blend_cntl; pipeline->cb_blend_control[i] = blend_cntl;
blend.blend_enable_4bit |= 0xfu << (i * 4);
} }
} }
@@ -1547,8 +1543,7 @@ radv_pipeline_uses_ds_feedback_loop(const VkGraphicsPipelineCreateInfo *pCreateI
static uint32_t static uint32_t
radv_compute_db_shader_control(const struct radv_graphics_pipeline *pipeline, radv_compute_db_shader_control(const struct radv_graphics_pipeline *pipeline,
const struct vk_graphics_pipeline_state *state, const struct vk_graphics_pipeline_state *state,
const VkGraphicsPipelineCreateInfo *pCreateInfo, const VkGraphicsPipelineCreateInfo *pCreateInfo)
const struct radv_blend_state *blend)
{ {
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
bool uses_ds_feedback_loop = radv_pipeline_uses_ds_feedback_loop(pCreateInfo, state); bool uses_ds_feedback_loop = radv_pipeline_uses_ds_feedback_loop(pCreateInfo, state);
@@ -1579,7 +1574,7 @@ radv_compute_db_shader_control(const struct radv_graphics_pipeline *pipeline,
bool export_conflict_wa = bool export_conflict_wa =
pipeline->base.device->physical_device->rad_info.has_export_conflict_bug && pipeline->base.device->physical_device->rad_info.has_export_conflict_bug &&
blend->blend_enable_4bit && radv_pipeline_is_blend_enabled(pipeline, state->cb) &&
(!state->ms || state->ms->rasterization_samples <= 1 || (!state->ms || state->ms->rasterization_samples <= 1 ||
(pipeline->dynamic_states & RADV_DYNAMIC_RASTERIZATION_SAMPLES)); (pipeline->dynamic_states & RADV_DYNAMIC_RASTERIZATION_SAMPLES));
@@ -1600,12 +1595,11 @@ radv_compute_db_shader_control(const struct radv_graphics_pipeline *pipeline,
static struct radv_depth_stencil_state static struct radv_depth_stencil_state
radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline, radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline,
const struct vk_graphics_pipeline_state *state, const struct vk_graphics_pipeline_state *state,
const VkGraphicsPipelineCreateInfo *pCreateInfo, const VkGraphicsPipelineCreateInfo *pCreateInfo)
const struct radv_blend_state *blend)
{ {
struct radv_depth_stencil_state ds_state = {0}; struct radv_depth_stencil_state ds_state = {0};
ds_state.db_shader_control = radv_compute_db_shader_control(pipeline, state, pCreateInfo, blend); ds_state.db_shader_control = radv_compute_db_shader_control(pipeline, state, pCreateInfo);
return ds_state; return ds_state;
} }
@@ -5239,7 +5233,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
radv_pipeline_init_dynamic_state(pipeline, &state); radv_pipeline_init_dynamic_state(pipeline, &state);
struct radv_depth_stencil_state ds_state = struct radv_depth_stencil_state ds_state =
radv_pipeline_init_depth_stencil_state(pipeline, &state, pCreateInfo, &blend); radv_pipeline_init_depth_stencil_state(pipeline, &state, pCreateInfo);
if (device->physical_device->rad_info.gfx_level >= GFX10_3) if (device->physical_device->rad_info.gfx_level >= GFX10_3)
gfx103_pipeline_init_vrs_state(pipeline, &state); gfx103_pipeline_init_vrs_state(pipeline, &state);