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radv: do not use radeon_set_context_reg_seq() for only one register

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radeon_set_context_reg() is a shortcut for that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12099>
This commit is contained in:
Samuel Pitoiset
2021-07-28 15:08:38 +02:00
parent f693b94d2f
commit 87b0962fef
2 changed files with 8 additions and 11 deletions
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9
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1728,8 +1728,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
radeon_emit(cmd_buffer->cs, 0);
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
cb->cb_color_base >> 32);
@@ -1956,12 +1955,10 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cs, ds_clear_value.stencil);
radeon_emit(cs, fui(ds_clear_value.depth));
} else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
radeon_emit(cs, fui(ds_clear_value.depth));
radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(ds_clear_value.depth));
} else {
assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
radeon_emit(cs, ds_clear_value.stencil);
radeon_set_context_reg(cs, R_028028_DB_STENCIL_CLEAR, ds_clear_value.stencil);
}
/* Update the ZRANGE_PRECISION value for the TC-compat bug. This is

10
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -542,11 +542,11 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
}
unsigned tmp = (unsigned)(1.0 * 8.0);
radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875 / 2)));
radeon_set_context_reg(cs, R_028A00_PA_SU_POINT_SIZE,
S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
radeon_set_context_reg(cs, R_028A04_PA_SU_POINT_MINMAX,
S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875 / 2)));
if (!has_clear_state) {
radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL, S_028004_ZPASS_INCREMENT_DISABLE(1));