turnip: split up gmem/tile alignment
Note: the x1/y1 align in tu6_emit_blit_scissor was broken Signed-off-by: Jonathan Marek <jonathan@marek.ca> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
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commit
86d1a4c907
@@ -123,7 +123,6 @@ force_sysmem(const struct tu_cmd_buffer *cmd,
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const struct VkRect2D *render_area)
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{
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const struct tu_framebuffer *fb = cmd->state.framebuffer;
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const struct tu_physical_device *device = cmd->device->physical_device;
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bool has_linear_mipmapped_store = false;
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const struct tu_render_pass *pass = cmd->state.pass;
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@@ -170,7 +169,7 @@ force_sysmem(const struct tu_cmd_buffer *cmd,
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* work around this, we force-enable sysmem rendering.
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*/
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const uint32_t y2 = render_area->offset.y + render_area->extent.height;
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const uint32_t aligned_y2 = ALIGN_POT(y2, device->tile_align_h);
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const uint32_t aligned_y2 = ALIGN_POT(y2, GMEM_ALIGN_H);
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return has_linear_mipmapped_store && aligned_y2 > fb->height;
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}
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@@ -180,9 +179,9 @@ tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
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const struct tu_device *dev,
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uint32_t pixels)
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{
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const uint32_t tile_align_w = dev->physical_device->tile_align_w;
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const uint32_t tile_align_h = dev->physical_device->tile_align_h;
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const uint32_t max_tile_width = 1024; /* A6xx */
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const uint32_t tile_align_w = 64; /* note: 32 when no input attachments */
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const uint32_t tile_align_h = 16;
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const uint32_t max_tile_width = 1024;
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/* note: don't offset the tiling config by render_area.offset,
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* because binning pass can't deal with it
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@@ -670,12 +669,11 @@ tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
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uint32_t x2 = x1 + render_area->extent.width - 1;
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uint32_t y2 = y1 + render_area->extent.height - 1;
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/* TODO: alignment requirement seems to be less than tile_align_w/h */
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if (align) {
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x1 = x1 & ~cmd->device->physical_device->tile_align_w;
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y1 = y1 & ~cmd->device->physical_device->tile_align_h;
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x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
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y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
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x1 = x1 & ~(GMEM_ALIGN_W - 1);
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y1 = y1 & ~(GMEM_ALIGN_H - 1);
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x2 = ALIGN_POT(x2 + 1, GMEM_ALIGN_W) - 1;
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y2 = ALIGN_POT(y2 + 1, GMEM_ALIGN_H) - 1;
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}
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tu_cs_emit_regs(cs,
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@@ -265,8 +265,6 @@ tu_physical_device_init(struct tu_physical_device *device,
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switch (device->gpu_id) {
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case 618:
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device->tile_align_w = 64;
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device->tile_align_h = 16;
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device->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
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device->ccu_offset_gmem = 0x7c000; /* 0x7e000 in some cases? */
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device->ccu_offset_bypass = 0x10000;
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@@ -275,8 +273,6 @@ tu_physical_device_init(struct tu_physical_device *device,
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break;
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case 630:
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case 640:
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device->tile_align_w = 64;
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device->tile_align_h = 16;
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device->magic.RB_UNKNOWN_8E04_blit = 0x01000000;
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device->ccu_offset_gmem = 0xf8000;
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device->ccu_offset_bypass = 0x20000;
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@@ -360,8 +360,6 @@ tu_GetRenderAreaGranularity(VkDevice _device,
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VkRenderPass renderPass,
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VkExtent2D *pGranularity)
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{
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TU_FROM_HANDLE(tu_device, device, _device);
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pGranularity->width = device->physical_device->tile_align_w;
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pGranularity->height = device->physical_device->tile_align_h;
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pGranularity->width = GMEM_ALIGN_W;
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pGranularity->height = GMEM_ALIGN_H;
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}
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@@ -314,10 +314,10 @@ struct tu_physical_device
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unsigned gpu_id;
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uint32_t gmem_size;
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uint64_t gmem_base;
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uint32_t tile_align_w;
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uint32_t tile_align_h;
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uint32_t ccu_offset_gmem;
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uint32_t ccu_offset_bypass;
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#define GMEM_ALIGN_W 16
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#define GMEM_ALIGN_H 4
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struct {
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uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
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