From 84de7a88d333318035e60f0fd40f284558a54d21 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 28 Jun 2022 13:51:42 -0700 Subject: [PATCH] intel/compiler/xe2: Emit texture instructions w/ combined LOD and array index The extra assertions are just there to help validate pack_lod_and_array_index (in nir_lower_tex.c). v2: Split got_lod_or_bias into two variables. This simplifies some changes that Sagar is working on. Suggested by Sagar. Reviewed-by: Sagar Ghuge Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 17 +++++++++++++++++ src/intel/compiler/brw_nir.c | 1 + 2 files changed, 18 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index c7d97e5a558..823cb070b93 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -8018,12 +8018,17 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_d(0); + ASSERTED bool got_lod = false; + ASSERTED bool got_bias = false; uint32_t header_bits = 0; for (unsigned i = 0; i < instr->num_srcs; i++) { nir_src nir_src = instr->src[i].src; fs_reg src = get_nir_src(ntb, nir_src); switch (instr->src[i].src_type) { case nir_tex_src_bias: + assert(!got_lod); + got_bias = true; + srcs[TEX_LOGICAL_SRC_LOD] = retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F); break; @@ -8051,6 +8056,9 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, srcs[TEX_LOGICAL_SRC_LOD2] = retype(src, BRW_REGISTER_TYPE_F); break; case nir_tex_src_lod: + assert(!got_bias); + got_lod = true; + switch (instr->op) { case nir_texop_txs: srcs[TEX_LOGICAL_SRC_LOD] = @@ -8142,6 +8150,15 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D); break; + case nir_tex_src_combined_lod_and_array_index_intel: + assert(!got_lod && !got_bias); + got_lod = true; + + assert(instr->op == nir_texop_txl || instr->op == nir_texop_txb); + srcs[TEX_LOGICAL_SRC_LOD] = + retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F); + break; + default: unreachable("unknown texture source"); } diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index a3bb7d666e2..0d100cbc07a 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -945,6 +945,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, .lower_offset_filter = devinfo->verx10 >= 125 ? lower_xehp_tg4_offset_filter : NULL, .lower_invalid_implicit_lod = true, + .pack_lod_and_array_index = devinfo->ver >= 20, }; /* In the case where TG4 coords are lowered to offsets and we have a