OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/compiler/xe2: Emit texture instructions w/ combined LOD and array index

Browse Source 
The extra assertions are just there to help validate
pack_lod_and_array_index (in nir_lower_tex.c).

v2: Split got_lod_or_bias into two variables. This simplifies some
changes that Sagar is working on. Suggested by Sagar.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27305>
This commit is contained in:
Ian Romanick
2022-06-28 13:51:42 -07:00
committed by Marge Bot
parent c8ba2bc2f0
commit 84de7a88d3
2 changed files with 18 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -8018,12 +8018,17 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_d(0);
ASSERTED bool got_lod = false;
ASSERTED bool got_bias = false;
uint32_t header_bits = 0;
for (unsigned i = 0; i < instr->num_srcs; i++) {
nir_src nir_src = instr->src[i].src;
fs_reg src = get_nir_src(ntb, nir_src);
switch (instr->src[i].src_type) {
case nir_tex_src_bias:
assert(!got_lod);
got_bias = true;
srcs[TEX_LOGICAL_SRC_LOD] =
retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F);
break;
@@ -8051,6 +8056,9 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
srcs[TEX_LOGICAL_SRC_LOD2] = retype(src, BRW_REGISTER_TYPE_F);
break;
case nir_tex_src_lod:
assert(!got_bias);
got_lod = true;
switch (instr->op) {
case nir_texop_txs:
srcs[TEX_LOGICAL_SRC_LOD] =
@@ -8142,6 +8150,15 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D);
break;
case nir_tex_src_combined_lod_and_array_index_intel:
assert(!got_lod && !got_bias);
got_lod = true;
assert(instr->op == nir_texop_txl || instr->op == nir_texop_txb);
srcs[TEX_LOGICAL_SRC_LOD] =
retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F);
break;
default:
unreachable("unknown texture source");
}

1
src/intel/compiler/brw_nir.c
View File

@@ -945,6 +945,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
.lower_offset_filter =
devinfo->verx10 >= 125 ? lower_xehp_tg4_offset_filter : NULL,
.lower_invalid_implicit_lod = true,
.pack_lod_and_array_index = devinfo->ver >= 20,
};
/* In the case where TG4 coords are lowered to offsets and we have a