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aco: don't use 32-bit fp inline constants for fp16 vop3p literals

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If we're applying the literal 0x3f800000 to a fp16 vop3p instruction, we
shouldn't use the 1.0 inline constant, because the hardware will use the
16-bit 1.0: 0x00003c00.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16296>
This commit is contained in:
Rhys Perry
2022-05-02 14:21:21 +01:00
committed by Marge Bot
parent 994f9b5a39
commit 84b404d34d
4 changed files with 16 additions and 8 deletions
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6
src/amd/compiler/aco_assembler.cpp
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@@ -88,7 +88,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
instr->operands.pop_back(); instr->operands.pop_back();
assert(instr->operands[1].isConstant()); assert(instr->operands[1].isConstant());
/* in case it's an inline constant, make it a literal */ /* in case it's an inline constant, make it a literal */
instr->operands[1].setFixed(PhysReg(255)); instr->operands[1] = Operand::literal32(instr->operands[1].constantValue());
} }
uint32_t opcode = ctx.opcode[(int)instr->opcode]; uint32_t opcode = ctx.opcode[(int)instr->opcode];
@@ -912,8 +912,8 @@ emit_long_jump(asm_context& ctx, SOPP_instruction* branch, bool backwards,
instr.reset(bld.sop1(aco_opcode::s_getpc_b64, branch->definitions[0]).instr); instr.reset(bld.sop1(aco_opcode::s_getpc_b64, branch->definitions[0]).instr);
emit_instruction(ctx, out, instr.get()); emit_instruction(ctx, out, instr.get());
instr.reset(bld.sop2(aco_opcode::s_addc_u32, def_tmp_lo, op_tmp_lo, Operand::zero()).instr); instr.reset(
instr->operands[1].setFixed(PhysReg{255}); /* this operand has to be a literal */ bld.sop2(aco_opcode::s_addc_u32, def_tmp_lo, op_tmp_lo, Operand::literal32(0)).instr);
emit_instruction(ctx, out, instr.get()); emit_instruction(ctx, out, instr.get());
branch->pass_flags = out.size(); branch->pass_flags = out.size();

11
src/amd/compiler/aco_ir.h
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@@ -644,6 +644,17 @@ public:
return op; return op;
} }
static Operand literal32(uint32_t v) noexcept
{
Operand op;
op.control_ = 0;
op.data_.i = v;
op.isConstant_ = true;
op.constSize = 2;
op.setFixed(PhysReg{255});
return op;
}
explicit Operand(RegClass type) noexcept explicit Operand(RegClass type) noexcept
{ {
isUndef_ = true; isUndef_ = true;

5
src/amd/compiler/aco_lower_to_hw_instr.cpp
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@@ -1973,10 +1973,7 @@ emit_set_mode(Builder& bld, float_mode new_mode, bool set_round, bool set_denorm
bld.sopp(aco_opcode::s_denorm_mode, -1, new_mode.denorm); bld.sopp(aco_opcode::s_denorm_mode, -1, new_mode.denorm);
} else if (set_round || set_denorm) { } else if (set_round || set_denorm) {
/* "((size - 1) << 11) | register" (MODE is encoded as register 1) */ /* "((size - 1) << 11) | register" (MODE is encoded as register 1) */
Instruction* instr = bld.sopk(aco_opcode::s_setreg_imm32_b32, Operand::literal32(new_mode.val), (7 << 11) | 1);
bld.sopk(aco_opcode::s_setreg_imm32_b32, Operand::c8(new_mode.val), (7 << 11) | 1).instr;
/* has to be a literal */
instr->operands[0].setFixed(PhysReg{255});
} }
} }

2
src/amd/compiler/aco_optimizer.cpp
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@@ -4595,7 +4595,7 @@ apply_literals(opt_ctx& ctx, aco_ptr<Instruction>& instr)
Operand op = instr->operands[i]; Operand op = instr->operands[i];
unsigned bits = get_operand_size(instr, i); unsigned bits = get_operand_size(instr, i);
if (op.isTemp() && ctx.info[op.tempId()].is_literal(bits) && ctx.uses[op.tempId()] == 0) { if (op.isTemp() && ctx.info[op.tempId()].is_literal(bits) && ctx.uses[op.tempId()] == 0) {
Operand literal = Operand::c32(ctx.info[op.tempId()].val); Operand literal = Operand::literal32(ctx.info[op.tempId()].val);
instr->format = withoutDPP(instr->format); instr->format = withoutDPP(instr->format);
if (instr->isVALU() && i > 0 && instr->format != Format::VOP3P) if (instr->isVALU() && i > 0 && instr->format != Format::VOP3P)
to_VOP3(ctx, instr); to_VOP3(ctx, instr);