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amd: remove some references to older LLVM versions in comments

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
This commit is contained in:
Marek Olšák
2021-04-13 21:37:40 -04:00
committed by Marge Bot
parent b878444c3a
commit 84895dba7f
6 changed files with 4 additions and 23 deletions
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2
src/amd/llvm/ac_llvm_util.c
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@@ -67,9 +67,7 @@ static void ac_init_llvm_target(void)
"mesa",
"-simplifycfg-sink-common=false",
"-global-isel-abort=2",
/* Atomic optimizations require LLVM 10.0 for gfx10 support. */
"-amdgpu-atomic-optimizations=true",
/* This was disabled by default in: https://reviews.llvm.org/D77228 */
"-structurizecfg-skip-uniform-regions",
};
LLVMParseCommandLineOptions(ARRAY_SIZE(argv), argv, NULL);

9
src/amd/llvm/ac_nir_to_llvm.c
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@@ -1730,8 +1730,6 @@ static void visit_store_ssbo(struct ac_nir_context *ctx, nir_intrinsic_instr *in
u_bit_scan_consecutive_range(&writemask, &start, &count);
/* Due to an LLVM limitation with LLVM < 9, split 3-element
* writes into a 2-element and a 1-element write. */
if (count == 3 && (elem_size_bytes != 4 || !ac_has_vec3_support(ctx->ac.chip_class, false))) {
writemask |= 1 << (start + 2);
count = 2;
@@ -2674,9 +2672,6 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx, const nir_int
if (cmpswap && instr->dest.ssa.bit_size == 64) {
result = emit_ssbo_comp_swap_64(ctx, params[2], params[3], params[1], params[0], true);
} else {
/* XXX: The new raw/struct atomic intrinsics are buggy
* with LLVM 8, see r358579.
*/
params[param_count++] = ctx->ac.i32_0; /* soffset */
params[param_count++] = ctx->ac.i32_0; /* slc */
@@ -5136,9 +5131,7 @@ bool ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class
NIR_PASS(progress, nir, nir_lower_vars_to_scratch, nir_var_function_temp, 256,
glsl_get_natural_size_align_bytes);
/* While it would be nice not to have this flag, we are constrained
* by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
*/
/* LLVM doesn't support VGPR indexing on GFX9. */
bool llvm_has_working_vgpr_indexing = chip_class != GFX9;
/* TODO: Indirect indexing of GS inputs is unimplemented.

2
src/gallium/drivers/radeonsi/si_get.c
View File

@@ -709,7 +709,7 @@ static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_sh
if (ir_type == PIPE_SHADER_IR_NATIVE)
return 256;
/* LLVM 10 only supports 1024 threads per block. */
/* LLVM only supports 1024 threads per block. */
return 1024;
}

4
src/gallium/drivers/radeonsi/si_pipe.c
View File

@@ -1266,9 +1266,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
sscreen->pbb_persistent_states_per_bin <= 32);
}
/* While it would be nice not to have this flag, we are constrained
* by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
*/
/* LLVM doesn't support VGPR indexing on GFX9. */
sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
(void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);

7
src/gallium/drivers/radeonsi/si_shader.c
View File

@@ -793,9 +793,6 @@ static bool si_shader_binary_open(struct si_screen *screen, struct si_shader *sh
if (sel && screen->info.chip_class >= GFX9 && !shader->is_gs_copy_shader &&
(sel->info.stage == MESA_SHADER_GEOMETRY || shader->key.as_ngg)) {
/* We add this symbol even on LLVM <= 8 to ensure that
* shader->config.lds_size is set correctly below.
*/
struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
sym->name = "esgs_ring";
sym->size = shader->gs_info.esgs_ring_size * 4;
@@ -1465,9 +1462,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi
if (!si_llvm_compile_shader(sscreen, compiler, shader, debug, nir, free_nir))
return false;
/* Validate SGPR and VGPR usage for compute to detect compiler bugs.
* LLVM 3.9svn has this bug.
*/
/* Validate SGPR and VGPR usage for compute to detect compiler bugs. */
if (sel->info.stage == MESA_SHADER_COMPUTE) {
unsigned wave_size = sscreen->compute_wave_size;
unsigned max_vgprs =

3
src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
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@@ -117,9 +117,6 @@ static void load_input_vs(struct si_shader_context *ctx, unsigned input_index, L
/* Use the open-coded implementation for all loads of doubles and
* of dword-sized data that needs fixups. We need to insert conversion
* code anyway, and the amd/common code does it for us.
*
* Note: On LLVM <= 8, we can only open-code formats with
* channel size >= 4 bytes.
*/
bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;