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radeonsi/vcn: Use ac_vcn_enc_init_cmds and AV1 defines from ac

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Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31113>
This commit is contained in:
David Rosca
2024-09-19 12:02:11 +02:00
committed by Marge Bot
parent 72ae8e25a8
commit 843608a9f4
5 changed files with 6 additions and 175 deletions
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2
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
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@@ -1759,6 +1759,8 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
enc->enc_pic.use_rc_per_pic_ex = false;
ac_vcn_enc_init_cmds(&enc->cmd, sscreen->info.vcn_ip_version);
if (sscreen->info.vcn_ip_version >= VCN_5_0_0) {
radeon_enc_5_0_init(enc);
if (sscreen->info.vcn_ip_version == VCN_5_0_0) {

58
src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
View File

@@ -17,36 +17,6 @@
#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
#define RENCODE_FW_INTERFACE_MINOR_VERSION 9
#define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
#define RENCODE_IB_PARAM_TASK_INFO 0x00000002
#define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
#define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
#define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
#define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
#define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
#define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
#define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
#define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
#define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
#define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
#define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
#define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
#define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
#define RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX 0x0000001d
#define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
#define RENCODE_IB_PARAM_QP_MAP 0x00000021
#define RENCODE_IB_PARAM_ENCODE_LATENCY 0x00000022
#define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000024
#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
#define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
#define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
#define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
#define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
#define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
#define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
static void radeon_enc_session_info(struct radeon_encoder *enc)
{
RADEON_ENC_BEGIN(enc->cmd.session_info);
@@ -1546,34 +1516,6 @@ void radeon_enc_1_2_init(struct radeon_encoder *enc)
enc->encode_params_codec_spec = radeon_enc_dummy;
}
enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
enc->cmd.rc_per_pic_ex = RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX;
enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
enc->cmd.enc_qp_map = RENCODE_IB_PARAM_QP_MAP;
enc->cmd.enc_latency = RENCODE_IB_PARAM_ENCODE_LATENCY;
enc->enc_pic.session_info.interface_version =
((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
(RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));

58
src/gallium/drivers/radeonsi/radeon_vcn_enc_2_0.c
View File

@@ -17,36 +17,6 @@
#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
#define RENCODE_FW_INTERFACE_MINOR_VERSION 1
#define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
#define RENCODE_IB_PARAM_TASK_INFO 0x00000002
#define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
#define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
#define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
#define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
#define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
#define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
#define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
#define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000b
#define RENCODE_IB_PARAM_INPUT_FORMAT 0x0000000c
#define RENCODE_IB_PARAM_OUTPUT_FORMAT 0x0000000d
#define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000f
#define RENCODE_IB_PARAM_INTRA_REFRESH 0x00000010
#define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
#define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
#define RENCODE_IB_PARAM_QP_MAP 0x00000014
#define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000015
#define RENCODE_IB_PARAM_ENCODE_LATENCY 0x00000018
#define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000019
#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
#define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
#define RENCODE_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
#define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
#define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
#define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
#define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
static void radeon_enc_op_preset(struct radeon_encoder *enc)
{
uint32_t preset_mode;
@@ -229,34 +199,6 @@ void radeon_enc_2_0_init(struct radeon_encoder *enc)
enc->spec_misc = radeon_enc_spec_misc_hevc;
}
enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
enc->cmd.enc_qp_map = RENCODE_IB_PARAM_QP_MAP;
enc->cmd.enc_latency = RENCODE_IB_PARAM_ENCODE_LATENCY;
enc->enc_pic.session_info.interface_version =
((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
(RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));

28
src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
View File

@@ -16,25 +16,6 @@
#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
#define RENCODE_FW_INTERFACE_MINOR_VERSION 15
#define RENCODE_IB_PARAM_CDF_DEFAULT_TABLE_BUFFER 0x00000019
#define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x0000001a
#define RENCODE_AV1_IB_PARAM_SPEC_MISC 0x00300001
#define RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION 0x00300002
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_END RENCODE_HEADER_INSTRUCTION_END
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY RENCODE_HEADER_INSTRUCTION_COPY
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV 0x00000005
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS 0x00000006
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER 0x00000007
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS 0x00000008
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_INFO 0x00000009
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS 0x0000000a
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS 0x0000000b
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS 0x0000000c
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE 0x0000000d
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU 0x0000000e
static void radeon_enc_sq_begin(struct radeon_encoder *enc)
{
rvcn_sq_header(&enc->cs, &enc->sq, true);
@@ -900,9 +881,9 @@ static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_h
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
/* tile_info */
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
radeon_enc_av1_bs_instruction_type(enc, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
/* quantization_params */
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
radeon_enc_av1_bs_instruction_type(enc, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
/* segmentation_enable */
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
radeon_enc_code_fixed_bits(enc, 0, 1);
@@ -1235,9 +1216,6 @@ void radeon_enc_4_0_init(struct radeon_encoder *enc)
enc->deblocking_filter = radeon_enc_dummy;
enc->tile_config = radeon_enc_dummy;
enc->encode_params_codec_spec = radeon_enc_dummy;
enc->cmd.cdf_default_table_av1 = RENCODE_IB_PARAM_CDF_DEFAULT_TABLE_BUFFER;
enc->cmd.bitstream_instruction_av1 = RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION;
enc->cmd.spec_misc_av1 = RENCODE_AV1_IB_PARAM_SPEC_MISC;
enc->spec_misc = radeon_enc_spec_misc_av1;
enc->encode_headers = radeon_enc_header_av1;
enc->obu_instructions = radeon_enc_obu_instruction;
@@ -1245,8 +1223,6 @@ void radeon_enc_4_0_init(struct radeon_encoder *enc)
enc->encode_params = radeon_enc_av1_encode_params;
}
enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
enc->enc_pic.session_info.interface_version =
((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
(RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));

35
src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c
View File

@@ -15,30 +15,6 @@
#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
#define RENCODE_FW_INTERFACE_MINOR_VERSION 3
#define RENCODE_REC_SWIZZLE_MODE_256B_D_VCN5 1
#define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
#define RENCODE_IB_PARAM_METADATA_BUFFER 0x0000001c
#define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER_OVERRIDE 0x0000001d
#define RENCODE_IB_PARAM_HEVC_ENCODE_PARAMS 0x00100004
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_END RENCODE_HEADER_INSTRUCTION_END
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY RENCODE_HEADER_INSTRUCTION_COPY
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV 0x00000005
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS 0x00000006
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER 0x00000007
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS 0x00000008
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID 0x00000009
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX 0x0000000a
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS 0x0000000b
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS 0x0000000c
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE 0x0000000d
#define RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU 0x0000000e
#define RENCODE_AV1_IB_PARAM_TILE_CONFIG 0x00300002
#define RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION 0x00300003
#define RENCODE_IB_PARAM_AV1_ENCODE_PARAMS 0x00300004
#define RENCODE_AV1_MIN_TILE_WIDTH 256
static void radeon_enc_cdf_default_table(struct radeon_encoder *enc)
@@ -712,7 +688,7 @@ static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
}
if (TileColsLog2 > 0 || TileRowsLog2 > 0) {
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID, 0);
radeon_enc_av1_bs_instruction_type(enc, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID, 0);
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
@@ -732,7 +708,7 @@ static void radeon_enc_av1_quantization_params(struct radeon_encoder *enc)
{
rvcn_enc_av1_spec_misc_t *p = &enc->enc_pic.av1_spec_misc;
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX, 0);
radeon_enc_av1_bs_instruction_type(enc, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX, 0);
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
@@ -1066,21 +1042,14 @@ void radeon_enc_5_0_init(struct radeon_encoder *enc)
} else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
enc->encode_params_codec_spec = radeon_enc_encode_params_hevc;
enc->spec_misc = radeon_enc_spec_misc_hevc;
enc->cmd.enc_params_hevc = RENCODE_IB_PARAM_HEVC_ENCODE_PARAMS;
} else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_AV1) {
enc->cdf_default_table = radeon_enc_cdf_default_table;
enc->spec_misc = radeon_enc_spec_misc_av1;
enc->tile_config = radeon_enc_tile_config_av1;
enc->obu_instructions = radeon_enc_obu_instruction;
enc->encode_params_codec_spec = radeon_enc_encode_params_av1;
enc->cmd.tile_config_av1 = RENCODE_AV1_IB_PARAM_TILE_CONFIG;
enc->cmd.bitstream_instruction_av1 = RENCODE_AV1_IB_PARAM_BITSTREAM_INSTRUCTION;
enc->cmd.enc_params_av1 = RENCODE_IB_PARAM_AV1_ENCODE_PARAMS;
}
enc->cmd.metadata = RENCODE_IB_PARAM_METADATA_BUFFER;
enc->cmd.ctx_override = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER_OVERRIDE;
enc->enc_pic.session_info.interface_version =
((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
(RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));