OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/compiler: Enable the emission of ROR/ROL instructions

Browse Source 
v2: 1) Drop changes for vec4 backend as on Gen11+ we don't support
       align16 mode (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Sagar Ghuge
2019-05-29 11:43:30 -07:00
parent 8d74749f81
commit 83fdec0f0d
6 changed files with 26 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -1796,6 +1796,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
case BRW_OPCODE_SHL:
brw_SHL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_ROL:
assert(devinfo->gen >= 11);
assert(src[0].type == dst.type);
brw_ROL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_ROR:
assert(devinfo->gen >= 11);
assert(src[0].type == dst.type);
brw_ROR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_F32TO16:
assert(devinfo->gen >= 7);
brw_F32TO16(p, dst, src[0]);