intel/compiler: Enable the emission of ROR/ROL instructions

v2: 1) Drop changes for vec4 backend as on Gen11+ we don't support align16 mode (Matt Turner) Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-05-29 11:43:30 -07:00
parent 8d74749f81
commit 83fdec0f0d
6 changed files with 26 additions and 2 deletions
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -594,6 +594,8 @@ namespace brw {
      ALU1(RNDE)
      ALU1(RNDU)
      ALU1(RNDZ)
+      ALU2(ROL)
+      ALU2(ROR)
      ALU2(SAD2)
      ALU2_ACC(SADA2)
      ALU2(SEL)