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radv: Set shared VGPR count in radv_postprocess_config.

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This commit allows RADV to set the shared VGPR count according to
the shader config.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Timur Kristóf
2019-09-13 15:53:09 +02:00
committed by Connor Abbott
parent 7bde4ddaf7
commit 83eebdb507
2 changed files with 18 additions and 2 deletions
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7
src/amd/vulkan/radv_pipeline.c
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@@ -4831,8 +4831,8 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline)
unsigned max_waves_per_sh = 0;
uint64_t va;
pipeline->cs.buf = malloc(20 * 4);
pipeline->cs.max_dw = 20;
pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
@@ -4844,6 +4844,9 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline)
radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
if (device->physical_device->rad_info.chip_class >= GFX10) {
radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
}
radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
S_00B860_WAVES(pipeline->max_waves) |