zink: implement ARB_instanced_arrays
this is just a simple case of connecting up the vertex state to the pipeline state Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6270>
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@@ -107,7 +107,7 @@ GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, soft
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GL_ARB_texture_rgb10_a2ui DONE (freedreno, swr, zink, panfrost)
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GL_ARB_texture_rgb10_a2ui DONE (freedreno, swr, zink, panfrost)
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GL_ARB_texture_swizzle DONE (freedreno, swr, v3d, zink, panfrost)
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GL_ARB_texture_swizzle DONE (freedreno, swr, v3d, zink, panfrost)
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GL_ARB_timer_query DONE (freedreno, swr)
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GL_ARB_timer_query DONE (freedreno, swr)
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GL_ARB_instanced_arrays DONE (freedreno, swr, v3d, panfrost)
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GL_ARB_instanced_arrays DONE (freedreno, swr, v3d, panfrost, zink)
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GL_ARB_vertex_type_2_10_10_10_rev DONE (freedreno, swr, v3d, panfrost)
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GL_ARB_vertex_type_2_10_10_10_rev DONE (freedreno, swr, v3d, panfrost)
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@@ -46,6 +46,14 @@ zink_create_gfx_pipeline(struct zink_screen *screen,
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vertex_input_state.pVertexAttributeDescriptions = state->element_state->attribs;
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vertex_input_state.pVertexAttributeDescriptions = state->element_state->attribs;
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vertex_input_state.vertexAttributeDescriptionCount = state->element_state->num_attribs;
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vertex_input_state.vertexAttributeDescriptionCount = state->element_state->num_attribs;
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VkPipelineVertexInputDivisorStateCreateInfoEXT vdiv_state = {};
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if (state->divisors_present) {
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vertex_input_state.pNext = &vdiv_state;
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vdiv_state.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT;
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vdiv_state.vertexBindingDivisorCount = state->divisors_present;
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vdiv_state.pVertexBindingDivisors = state->divisors;
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}
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VkPipelineInputAssemblyStateCreateInfo primitive_state = {};
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VkPipelineInputAssemblyStateCreateInfo primitive_state = {};
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primitive_state.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO;
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primitive_state.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO;
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primitive_state.topology = primitive_topology;
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primitive_state.topology = primitive_topology;
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@@ -41,6 +41,8 @@ struct zink_gfx_pipeline_state {
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struct zink_vertex_elements_hw_state *element_state;
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struct zink_vertex_elements_hw_state *element_state;
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VkVertexInputBindingDescription bindings[PIPE_MAX_ATTRIBS]; // combination of element_state and stride
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VkVertexInputBindingDescription bindings[PIPE_MAX_ATTRIBS]; // combination of element_state and stride
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VkVertexInputBindingDivisorDescriptionEXT divisors[PIPE_MAX_ATTRIBS];
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uint8_t divisors_present;
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uint32_t num_attachments;
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uint32_t num_attachments;
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struct zink_blend_state *blend_state;
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struct zink_blend_state *blend_state;
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@@ -98,6 +98,9 @@ zink_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TGSI_TEXCOORD:
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case PIPE_CAP_TGSI_TEXCOORD:
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return 1;
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return 1;
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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return screen->have_EXT_vertex_attribute_divisor;
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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if (!screen->feats.dualSrcBlend)
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if (!screen->feats.dualSrcBlend)
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return 0;
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return 0;
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@@ -48,7 +48,6 @@ zink_create_vertex_elements_state(struct pipe_context *pctx,
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int num_bindings = 0;
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int num_bindings = 0;
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for (i = 0; i < num_elements; ++i) {
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for (i = 0; i < num_elements; ++i) {
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const struct pipe_vertex_element *elem = elements + i;
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const struct pipe_vertex_element *elem = elements + i;
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assert(!elem->instance_divisor);
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int binding = elem->vertex_buffer_index;
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int binding = elem->vertex_buffer_index;
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if (buffer_map[binding] < 0) {
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if (buffer_map[binding] < 0) {
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@@ -59,7 +58,11 @@ zink_create_vertex_elements_state(struct pipe_context *pctx,
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ves->bindings[binding].binding = binding;
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ves->bindings[binding].binding = binding;
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ves->bindings[binding].inputRate = VK_VERTEX_INPUT_RATE_VERTEX;
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ves->bindings[binding].inputRate = elem->instance_divisor ? VK_VERTEX_INPUT_RATE_INSTANCE : VK_VERTEX_INPUT_RATE_VERTEX;
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assert(!elem->instance_divisor || zink_screen(pctx->screen)->have_EXT_vertex_attribute_divisor);
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ves->divisor[binding] = elem->instance_divisor;
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assert(elem->instance_divisor <= screen->max_vertex_attrib_divisor);
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ves->hw_state.attribs[i].binding = binding;
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ves->hw_state.attribs[i].binding = binding;
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ves->hw_state.attribs[i].location = i; // TODO: unsure
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ves->hw_state.attribs[i].location = i; // TODO: unsure
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@@ -82,12 +85,18 @@ zink_bind_vertex_elements_state(struct pipe_context *pctx,
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struct zink_gfx_pipeline_state *state = &ctx->gfx_pipeline_state;
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struct zink_gfx_pipeline_state *state = &ctx->gfx_pipeline_state;
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ctx->element_state = cso;
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ctx->element_state = cso;
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state->hash = 0;
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state->hash = 0;
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state->divisors_present = 0;
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if (cso) {
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if (cso) {
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state->element_state = &ctx->element_state->hw_state;
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state->element_state = &ctx->element_state->hw_state;
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struct zink_vertex_elements_state *ves = cso;
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struct zink_vertex_elements_state *ves = cso;
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for (int i = 0; i < state->element_state->num_bindings; ++i) {
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for (int i = 0; i < state->element_state->num_bindings; ++i) {
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state->bindings[i].binding = ves->bindings[i].binding;
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state->bindings[i].binding = ves->bindings[i].binding;
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state->bindings[i].inputRate = ves->bindings[i].inputRate;
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state->bindings[i].inputRate = ves->bindings[i].inputRate;
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if (ves->divisor[i]) {
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state->divisors[state->divisors_present].divisor = ves->divisor[i];
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state->divisors[state->divisors_present].binding = state->bindings[i].binding;
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state->divisors_present++;
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}
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}
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}
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} else
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} else
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state->element_state = NULL;
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state->element_state = NULL;
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@@ -38,6 +38,7 @@ struct zink_vertex_elements_state {
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uint32_t binding;
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uint32_t binding;
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VkVertexInputRate inputRate;
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VkVertexInputRate inputRate;
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} bindings[PIPE_MAX_ATTRIBS];
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} bindings[PIPE_MAX_ATTRIBS];
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uint32_t divisor[PIPE_MAX_ATTRIBS];
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uint8_t binding_map[PIPE_MAX_ATTRIBS];
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uint8_t binding_map[PIPE_MAX_ATTRIBS];
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struct zink_vertex_elements_hw_state hw_state;
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struct zink_vertex_elements_hw_state hw_state;
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};
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};
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