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r600: ensure that the last vertex is always processed on evergreen

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This situation is happening, for instance, when the hardware is
using the type FMT_8_8_8_8 (4 bytes) while the software was
requesting a 3 bytes type. The width should be adjusted to the
expected hardware size; otherwise, the last vertex is lost.

Note: The rv770 didn't behave like this. This is definitely
a hardware change between these gpus.

This change was tested on palm and cayman. Here are the tests fixed:
spec/!opengl 2.0/gl-2.0-vertexattribpointer-size-3: fail pass
deqp-gles2/functional/draw/random/62: fail pass
deqp-gles2/functional/vertex_arrays/single_attribute/strides/buffer_0_32_byte3_vec4_dynamic_draw_quads_1: fail pass
deqp-gles2/functional/vertex_arrays/single_attribute/strides/buffer_0_32_short3_vec4_dynamic_draw_quads_1: fail pass
deqp-gles2/functional/vertex_arrays/single_attribute/strides/buffer_0_32_short3_vec4_dynamic_draw_quads_256: fail pass
deqp-gles3/functional/draw/random/117: fail pass
deqp-gles3/functional/vertex_arrays/single_attribute/strides/byte/buffer_stride32_components3_quads1: fail pass
deqp-gles3/functional/vertex_arrays/single_attribute/strides/short/buffer_stride32_components3_quads1: fail pass
deqp-gles3/functional/vertex_arrays/single_attribute/strides/short/buffer_stride32_components3_quads256: fail pass

Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32184>
This commit is contained in:
Patrick Lerda
2024-11-15 20:21:46 +01:00
committed by Marge Bot
parent 275535774c
commit 81889f4d5c
3 changed files with 13 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/r600/evergreen_state.c
View File

@@ -2142,7 +2142,7 @@ static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
radeon_emit(cs, (resource_offset + buffer_index) * 8);
radeon_emit(cs, va); /* RESOURCEi_WORD0 */
radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1 + shader->width_correction[buffer_index]); /* RESOURCEi_WORD1 */
radeon_emit(cs, /* RESOURCEi_WORD2 */
S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
S_030008_STRIDE(stride) |

1
src/gallium/drivers/r600/r600_pipe.h
View File

@@ -417,6 +417,7 @@ struct r600_fetch_shader {
unsigned offset;
uint32_t buffer_mask;
unsigned strides[PIPE_MAX_ATTRIBS];
uint8_t width_correction[PIPE_MAX_ATTRIBS];
};
struct r600_shader_state {

11
src/gallium/drivers/r600/r600_shader.c
View File

@@ -436,6 +436,17 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
if (unlikely(r = r600_bytecode_add_vtx(&bc, &vtx)))
goto fail;
if (unlikely(rctx->b.gfx_level >= EVERGREEN &&
desc->nr_channels == 3 &&
(format == FMT_8_8_8_8 ||
format == FMT_16_16_16_16 ||
format == FMT_16_16_16_16_FLOAT))) {
if (format == FMT_8_8_8_8)
shader->width_correction[elements[i].vertex_buffer_index] = 4 - 3;
else
shader->width_correction[elements[i].vertex_buffer_index] = 8 - 6;
}
}
r600_bytecode_add_cfinst(&bc, CF_OP_RET);