anv: Allocate surface states per-subpass
Instead of allocating surface states for attachments in BeginRenderPass, we now allocate them in begin_subpass. Also, since we're zeroing things, we can be a bit cleaner about or implementation and just fill out all those passes for which we have allocated surface states. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
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814dc66935
@@ -2748,11 +2748,11 @@ struct anv_cmd_state {
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* flat array. For depth-stencil attachments, the surface state is simply
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* left blank.
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*/
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struct anv_state render_pass_states;
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struct anv_state attachment_states;
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/**
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* A null surface state of the right size to match the framebuffer. This
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* is one of the states in render_pass_states.
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* is one of the states in attachment_states.
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*/
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struct anv_state null_surface_state;
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};
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@@ -501,19 +501,6 @@ depth_stencil_attachment_compute_aux_usage(struct anv_device *device,
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att_state->fast_clear = true;
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}
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static bool
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need_input_attachment_state(const struct anv_render_pass_attachment *att)
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{
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if (!(att->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT))
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return false;
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/* We only allocate input attachment states for color surfaces. Compression
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* is not yet enabled for depth textures and stencil doesn't allow
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* compression so we can just use the texture surface state from the view.
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*/
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return vk_format_is_color(att->format);
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}
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#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
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#if GEN_GEN == 12
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@@ -1474,110 +1461,77 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer,
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*/
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static VkResult
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genX(cmd_buffer_alloc_att_surf_states)(struct anv_cmd_buffer *cmd_buffer,
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const struct anv_render_pass *pass)
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const struct anv_render_pass *pass,
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const struct anv_subpass *subpass)
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{
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const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
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struct anv_cmd_state *state = &cmd_buffer->state;
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/* Reserve one for the NULL state. */
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unsigned num_states = 1;
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for (uint32_t i = 0; i < pass->attachment_count; ++i) {
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if (vk_format_is_color(pass->attachments[i].format))
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num_states++;
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for (uint32_t i = 0; i < subpass->attachment_count; i++) {
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uint32_t att = subpass->attachments[i].attachment;
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if (att == VK_ATTACHMENT_UNUSED)
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continue;
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if (need_input_attachment_state(&pass->attachments[i]))
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assert(att < pass->attachment_count);
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if (!vk_format_is_color(pass->attachments[att].format))
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continue;
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const VkImageUsageFlagBits att_usage = subpass->attachments[i].usage;
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assert(util_bitcount(att_usage) == 1);
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if (att_usage == VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT ||
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att_usage == VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
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num_states++;
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}
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const uint32_t ss_stride = align_u32(isl_dev->ss.size, isl_dev->ss.align);
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state->render_pass_states =
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state->attachment_states =
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anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
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num_states * ss_stride, isl_dev->ss.align);
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if (state->render_pass_states.map == NULL) {
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if (state->attachment_states.map == NULL) {
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return anv_batch_set_error(&cmd_buffer->batch,
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VK_ERROR_OUT_OF_DEVICE_MEMORY);
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}
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struct anv_state next_state = state->render_pass_states;
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struct anv_state next_state = state->attachment_states;
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next_state.alloc_size = isl_dev->ss.size;
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state->null_surface_state = next_state;
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next_state.offset += ss_stride;
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next_state.map += ss_stride;
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for (uint32_t i = 0; i < pass->attachment_count; ++i) {
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if (vk_format_is_color(pass->attachments[i].format)) {
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state->attachments[i].color.state = next_state;
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for (uint32_t i = 0; i < subpass->attachment_count; i++) {
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uint32_t att = subpass->attachments[i].attachment;
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if (att == VK_ATTACHMENT_UNUSED)
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continue;
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assert(att < pass->attachment_count);
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if (!vk_format_is_color(pass->attachments[att].format))
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continue;
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const VkImageUsageFlagBits att_usage = subpass->attachments[i].usage;
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assert(util_bitcount(att_usage) == 1);
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if (att_usage == VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
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state->attachments[att].color.state = next_state;
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else if (att_usage == VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
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state->attachments[att].input.state = next_state;
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else
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continue;
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state->attachments[att].color.state = next_state;
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next_state.offset += ss_stride;
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next_state.map += ss_stride;
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}
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if (need_input_attachment_state(&pass->attachments[i])) {
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state->attachments[i].input.state = next_state;
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next_state.offset += ss_stride;
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next_state.map += ss_stride;
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}
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}
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assert(next_state.offset == state->render_pass_states.offset +
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state->render_pass_states.alloc_size);
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assert(next_state.offset == state->attachment_states.offset +
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state->attachment_states.alloc_size);
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return VK_SUCCESS;
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}
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static void
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genX(cmd_buffer_fill_att_surf_states)(struct anv_cmd_buffer *cmd_buffer,
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const struct anv_render_pass *pass,
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const struct anv_framebuffer *framebuffer)
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{
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const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
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struct anv_cmd_state *state = &cmd_buffer->state;
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isl_null_fill_state(isl_dev, state->null_surface_state.map,
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isl_extent3d(framebuffer->width,
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framebuffer->height,
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framebuffer->layers));
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for (uint32_t i = 0; i < pass->attachment_count; ++i) {
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struct anv_image_view *iview = state->attachments[i].image_view;
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union isl_color_value clear_color = { .u32 = { 0, } };
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if (vk_format_is_color(pass->attachments[i].format)) {
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if (state->attachments[i].fast_clear) {
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anv_clear_color_from_att_state(&clear_color,
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&state->attachments[i], iview);
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}
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anv_image_fill_surface_state(cmd_buffer->device,
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iview->image,
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VK_IMAGE_ASPECT_COLOR_BIT,
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&iview->planes[0].isl,
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ISL_SURF_USAGE_RENDER_TARGET_BIT,
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state->attachments[i].aux_usage,
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&clear_color,
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0,
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&state->attachments[i].color,
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NULL);
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add_surface_state_relocs(cmd_buffer, state->attachments[i].color);
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}
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if (need_input_attachment_state(&pass->attachments[i])) {
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anv_image_fill_surface_state(cmd_buffer->device,
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iview->image,
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VK_IMAGE_ASPECT_COLOR_BIT,
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&iview->planes[0].isl,
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ISL_SURF_USAGE_TEXTURE_BIT,
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state->attachments[i].input_aux_usage,
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&clear_color,
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0,
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&state->attachments[i].input,
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NULL);
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add_surface_state_relocs(cmd_buffer, state->attachments[i].input);
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}
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}
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}
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VkResult
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genX(BeginCommandBuffer)(
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VkCommandBuffer commandBuffer,
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@@ -1659,7 +1613,8 @@ genX(BeginCommandBuffer)(
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if (result != VK_SUCCESS)
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return result;
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result = genX(cmd_buffer_alloc_att_surf_states)(cmd_buffer, pass);
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result = genX(cmd_buffer_alloc_att_surf_states)(cmd_buffer, pass,
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subpass);
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if (result != VK_SUCCESS)
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return result;
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@@ -1825,8 +1780,8 @@ genX(CmdExecuteCommands)(
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*/
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struct anv_bo *ss_bo =
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primary->device->surface_state_pool.block_pool.bo;
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struct anv_state src_state = primary->state.render_pass_states;
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struct anv_state dst_state = secondary->state.render_pass_states;
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struct anv_state src_state = primary->state.attachment_states;
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struct anv_state dst_state = secondary->state.attachment_states;
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assert(src_state.alloc_size == dst_state.alloc_size);
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genX(cmd_buffer_so_memcpy)(primary,
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@@ -5005,7 +4960,8 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
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uint32_t subpass_id)
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{
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struct anv_cmd_state *cmd_state = &cmd_buffer->state;
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struct anv_subpass *subpass = &cmd_state->pass->subpasses[subpass_id];
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struct anv_render_pass *pass = cmd_state->pass;
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struct anv_subpass *subpass = &pass->subpasses[subpass_id];
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cmd_state->subpass = subpass;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
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@@ -5261,25 +5217,6 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
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assert(att_state->pending_clear_aspects == 0);
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}
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if (GEN_GEN < 10 &&
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(att_state->pending_load_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) &&
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image->planes[0].aux_usage != ISL_AUX_USAGE_NONE &&
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iview->planes[0].isl.base_level == 0 &&
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iview->planes[0].isl.base_array_layer == 0) {
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if (att_state->aux_usage != ISL_AUX_USAGE_NONE) {
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genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color.state,
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image, VK_IMAGE_ASPECT_COLOR_BIT,
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false /* copy to ss */);
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}
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if (need_input_attachment_state(&cmd_state->pass->attachments[a]) &&
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att_state->input_aux_usage != ISL_AUX_USAGE_NONE) {
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genX(copy_fast_clear_dwords)(cmd_buffer, att_state->input.state,
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image, VK_IMAGE_ASPECT_COLOR_BIT,
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false /* copy to ss */);
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}
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}
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/* If multiview is enabled, then we are only done clearing when we no
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* longer have pending layers to clear, or when we have processed the
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* last subpass that uses this attachment.
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@@ -5293,6 +5230,83 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
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att_state->pending_load_aspects = 0;
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}
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/* We've transitioned all our images possibly fast clearing them. Now we
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* can fill out the surface states that we will use as render targets
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* during actual subpass rendering.
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*/
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VkResult result = genX(cmd_buffer_alloc_att_surf_states)(cmd_buffer,
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pass, subpass);
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if (result != VK_SUCCESS)
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return;
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isl_null_fill_state(&cmd_buffer->device->isl_dev,
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cmd_state->null_surface_state.map,
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isl_extent3d(fb->width, fb->height, fb->layers));
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for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
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const uint32_t att = subpass->attachments[i].attachment;
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if (att == VK_ATTACHMENT_UNUSED)
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continue;
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assert(att < cmd_state->pass->attachment_count);
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struct anv_render_pass_attachment *pass_att = &pass->attachments[att];
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struct anv_attachment_state *att_state = &cmd_state->attachments[att];
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struct anv_image_view *iview = att_state->image_view;
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if (!vk_format_is_color(pass_att->format))
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continue;
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const VkImageUsageFlagBits att_usage = subpass->attachments[i].usage;
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assert(util_bitcount(att_usage) == 1);
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struct anv_surface_state *surface_state;
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isl_surf_usage_flags_t isl_surf_usage;
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enum isl_aux_usage isl_aux_usage;
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if (att_usage == VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) {
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surface_state = &att_state->color;
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isl_surf_usage = ISL_SURF_USAGE_RENDER_TARGET_BIT;
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isl_aux_usage = att_state->aux_usage;
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} else if (att_usage == VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
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surface_state = &att_state->input;
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isl_surf_usage = ISL_SURF_USAGE_TEXTURE_BIT;
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isl_aux_usage = att_state->input_aux_usage;
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} else {
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continue;
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}
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/* We had better have a surface state when we get here */
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assert(surface_state->state.map);
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union isl_color_value clear_color = { .u32 = { 0, } };
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if (pass_att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR &&
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att_state->fast_clear)
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anv_clear_color_from_att_state(&clear_color, att_state, iview);
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anv_image_fill_surface_state(cmd_buffer->device,
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iview->image,
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VK_IMAGE_ASPECT_COLOR_BIT,
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&iview->planes[0].isl,
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isl_surf_usage,
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isl_aux_usage,
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&clear_color,
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0,
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surface_state,
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NULL);
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add_surface_state_relocs(cmd_buffer, *surface_state);
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if (GEN_GEN < 10 &&
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pass_att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD &&
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iview->image->planes[0].aux_usage != ISL_AUX_USAGE_NONE &&
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iview->planes[0].isl.base_level == 0 &&
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iview->planes[0].isl.base_array_layer == 0) {
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genX(copy_fast_clear_dwords)(cmd_buffer, surface_state->state,
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iview->image,
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VK_IMAGE_ASPECT_COLOR_BIT,
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false /* copy to ss */);
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}
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}
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#if GEN_GEN >= 11
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/* The PIPE_CONTROL command description says:
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*
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@@ -5350,6 +5364,19 @@ cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer)
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uint32_t subpass_id = anv_get_subpass_id(&cmd_buffer->state);
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struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
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/* We are done with the previous subpass and all rendering directly to that
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* subpass is now complete. Zero out all the surface states so we don't
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* accidentally use them between now and the next subpass.
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*/
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for (uint32_t i = 0; i < cmd_state->pass->attachment_count; ++i) {
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memset(&cmd_state->attachments[i].color, 0,
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sizeof(cmd_state->attachments[i].color));
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memset(&cmd_state->attachments[i].input, 0,
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sizeof(cmd_state->attachments[i].input));
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}
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cmd_state->null_surface_state = ANV_STATE_NULL;
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cmd_state->attachment_states = ANV_STATE_NULL;
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for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
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const uint32_t a = subpass->attachments[i].attachment;
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if (a == VK_ATTACHMENT_UNUSED)
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@@ -5766,14 +5793,6 @@ void genX(CmdBeginRenderPass)(
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return;
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}
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result = genX(cmd_buffer_alloc_att_surf_states)(cmd_buffer, pass);
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if (result != VK_SUCCESS) {
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assert(anv_batch_has_error(&cmd_buffer->batch));
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return;
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}
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genX(cmd_buffer_fill_att_surf_states)(cmd_buffer, pass, framebuffer);
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genX(flush_pipeline_select_3d)(cmd_buffer);
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cmd_buffer_begin_subpass(cmd_buffer, 0);
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