nir: Rename Boolean-related opcodes to include 32 in the name
This is a squash of a bunch of individual changes: nir/builder: Generate 32-bit bool opcodes transparently nir/algebraic: Remap Boolean opcodes to the 32-bit variant Use 32-bit opcodes in the NIR producers and optimizations Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c Use 32-bit opcodes in the NIR back-ends Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:

committed by
Jason Ekstrand

parent
b569093566
commit
80e8dfe9de
@@ -1004,24 +1004,24 @@ ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
|
||||
enum qpu_cond cond;
|
||||
|
||||
switch (compare_instr->op) {
|
||||
case nir_op_feq:
|
||||
case nir_op_ieq:
|
||||
case nir_op_feq32:
|
||||
case nir_op_ieq32:
|
||||
case nir_op_seq:
|
||||
cond = QPU_COND_ZS;
|
||||
break;
|
||||
case nir_op_fne:
|
||||
case nir_op_ine:
|
||||
case nir_op_fne32:
|
||||
case nir_op_ine32:
|
||||
case nir_op_sne:
|
||||
cond = QPU_COND_ZC;
|
||||
break;
|
||||
case nir_op_fge:
|
||||
case nir_op_ige:
|
||||
case nir_op_uge:
|
||||
case nir_op_fge32:
|
||||
case nir_op_ige32:
|
||||
case nir_op_uge32:
|
||||
case nir_op_sge:
|
||||
cond = QPU_COND_NC;
|
||||
break;
|
||||
case nir_op_flt:
|
||||
case nir_op_ilt:
|
||||
case nir_op_flt32:
|
||||
case nir_op_ilt32:
|
||||
case nir_op_slt:
|
||||
cond = QPU_COND_NS;
|
||||
break;
|
||||
@@ -1048,7 +1048,7 @@ ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
|
||||
qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
|
||||
break;
|
||||
|
||||
case nir_op_bcsel:
|
||||
case nir_op_b32csel:
|
||||
*dest = qir_SEL(c, cond,
|
||||
ntq_get_alu_src(c, sel_instr, 1),
|
||||
ntq_get_alu_src(c, sel_instr, 2));
|
||||
@@ -1264,21 +1264,21 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
|
||||
case nir_op_sne:
|
||||
case nir_op_sge:
|
||||
case nir_op_slt:
|
||||
case nir_op_feq:
|
||||
case nir_op_fne:
|
||||
case nir_op_fge:
|
||||
case nir_op_flt:
|
||||
case nir_op_ieq:
|
||||
case nir_op_ine:
|
||||
case nir_op_ige:
|
||||
case nir_op_uge:
|
||||
case nir_op_ilt:
|
||||
case nir_op_feq32:
|
||||
case nir_op_fne32:
|
||||
case nir_op_fge32:
|
||||
case nir_op_flt32:
|
||||
case nir_op_ieq32:
|
||||
case nir_op_ine32:
|
||||
case nir_op_ige32:
|
||||
case nir_op_uge32:
|
||||
case nir_op_ilt32:
|
||||
if (!ntq_emit_comparison(c, &result, instr, instr)) {
|
||||
fprintf(stderr, "Bad comparison instruction\n");
|
||||
}
|
||||
break;
|
||||
|
||||
case nir_op_bcsel:
|
||||
case nir_op_b32csel:
|
||||
result = ntq_emit_bcsel(c, instr, src);
|
||||
break;
|
||||
case nir_op_fcsel:
|
||||
|
Reference in New Issue
Block a user