diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c b/src/gallium/drivers/etnaviv/etnaviv_state.c
index 794e6820995..6b17ad9131c 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_state.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
@@ -718,12 +718,26 @@ etna_update_zsa(struct etna_context *ctx)
    struct etna_zsa_state *zsa = etna_zsa_state(zsa_state);
    struct etna_screen *screen = ctx->screen;
    uint32_t new_pe_depth, new_ra_depth;
+   bool early_z_allowed = !VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z);
    bool late_z_write = false, early_z_write = false,
         late_z_test = false, early_z_test = false;
 
+   /* Linear PE breaks the combination of early test with late write, as it
+    * seems RA and PE disagree about the buffer layout in this mode. Fall back
+    * to late Z always even though early Z write might be possible, as we don't
+    * know if any other draws to the same surface require late Z write.
+    */
+   if (ctx->framebuffer_s.nr_cbufs > 0) {
+      struct etna_surface *cbuf = etna_surface(ctx->framebuffer_s.cbufs[0]);
+      struct etna_resource *res = etna_resource(cbuf->base.texture);
+
+      if (res->layout == ETNA_LAYOUT_LINEAR)
+         early_z_allowed = false;
+   }
+
    if (zsa->z_write_enabled) {
       if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH) &&
-          !VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z) &&
+          early_z_allowed &&
           !zsa->stencil_enabled &&
           !zsa_state->alpha_enabled &&
           !shader_state->writes_z &&
@@ -734,7 +748,7 @@ etna_update_zsa(struct etna_context *ctx)
    }
 
    if (zsa->z_test_enabled) {
-      if (!VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z) &&
+      if (early_z_allowed &&
           !zsa->stencil_modified &&
           !shader_state->writes_z)
          early_z_test = true;
@@ -742,20 +756,6 @@ etna_update_zsa(struct etna_context *ctx)
          late_z_test = true;
    }
 
-   /* Linear PE breaks the combination of early test with late write, as it
-    * seems RA and PE disagree about the cache layout in this mode. Switch to
-    * late test to work around this issue.
-    */
-   if (ctx->framebuffer_s.nr_cbufs > 0) {
-      struct etna_surface *cbuf = etna_surface(ctx->framebuffer_s.cbufs[0]);
-      struct etna_resource *res = etna_resource(cbuf->base.texture);
-
-      if (res->layout == ETNA_LAYOUT_LINEAR && early_z_test && late_z_write) {
-         early_z_test = false;
-         late_z_test = true;
-      }
-   }
-
    new_pe_depth = VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(zsa->z_test_enabled ?
                      /* compare funcs have 1 to 1 mapping */
                      zsa_state->depth_func : PIPE_FUNC_ALWAYS) |