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nir: Handle divergence for decl_reg

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Once decl_reg is handled, src[0].ssa->divergent will be properly set, so
load_reg and load_reg_indirect do not need special treatment.

shader-db can run to completion on HSW, IVB, and SNB now. No other
testing was done.

v2: Refactor nir_intrinsic_load_reg and nir_intrinsic_load_reg_indirect
handling. Suggested by Daniel Schürmann.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 4fd257d20f ("nir: Properly handle divergence for load_reg")
Fixes: 6dbb5f1e07 ("intel/fs: rerun divergence analysis prior to convert_from_ssa")
Closes: #10233
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26436>
This commit is contained in:
Ian Romanick
2023-11-30 13:30:53 -08:00
committed by Marge Bot
parent 7cd0553572
commit 7fce0a5598
1 changed files with 5 additions and 8 deletions
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13
src/compiler/nir/nir_divergence_analysis.c
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@@ -219,14 +219,9 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
is_divergent = false;
break;
case nir_intrinsic_load_reg:
case nir_intrinsic_load_reg_indirect: {
nir_intrinsic_instr *decl = nir_reg_get_decl(instr->src[0].ssa);
is_divergent = nir_intrinsic_divergent(decl);
if (instr->intrinsic == nir_intrinsic_load_reg_indirect)
is_divergent |= instr->src[1].ssa->divergent;
case nir_intrinsic_decl_reg:
is_divergent = nir_intrinsic_divergent(instr);
break;
}
/* Intrinsics with divergence depending on shader stage and hardware */
case nir_intrinsic_load_shader_record_ptr:
@@ -465,7 +460,9 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_desc_set_dynamic_index_intel:
case nir_intrinsic_load_global_constant_bounded:
case nir_intrinsic_load_global_constant_offset:
case nir_intrinsic_resource_intel: {
case nir_intrinsic_resource_intel:
case nir_intrinsic_load_reg:
case nir_intrinsic_load_reg_indirect: {
unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
for (unsigned i = 0; i < num_srcs; i++) {
if (instr->src[i].ssa->divergent) {