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intel/compiler: construct masks instead of using magic values

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Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23933>
This commit is contained in:
Rohan Garg
2023-06-28 15:37:26 +02:00
committed by Marge Bot
parent 0925b07f4f
commit 7f48c70bab
1 changed files with 2 additions and 2 deletions
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4
src/intel/compiler/brw_fs_nir.cpp
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@@ -5420,7 +5420,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
const fs_builder ubld = bld.exec_all().group(1, 0);
fs_reg handle = component(ubld.vgrf(BRW_REGISTER_TYPE_UD), 0);
ubld.AND(handle, retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
brw_imm_ud(~0x3ffu));
brw_imm_ud(INTEL_MASK(31, 10)));
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS);
srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle;
} else if (devinfo->ver >= 8) {
@@ -5487,7 +5487,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
const fs_builder ubld = bld.exec_all().group(1, 0);
fs_reg handle = component(ubld.vgrf(BRW_REGISTER_TYPE_UD), 0);
ubld.AND(handle, retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
brw_imm_ud(~0x3ffu));
brw_imm_ud(INTEL_MASK(31, 10)));
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS);
srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle;
} else if (devinfo->ver >= 8) {