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nir: add nir_intrinsic_load_sample_positions_amd

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This will be used to lower barycentric_at_sample in NIR for RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
This commit is contained in:
Samuel Pitoiset
2022-09-15 14:55:10 +02:00
committed by Marge Bot
parent 266fe31666
commit 7f444fc72c
2 changed files with 4 additions and 0 deletions
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1
src/compiler/nir/nir_divergence_analysis.c
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@@ -154,6 +154,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_ring_es2gs_offset_amd: case nir_intrinsic_load_ring_es2gs_offset_amd:
case nir_intrinsic_load_ring_task_draw_amd: case nir_intrinsic_load_ring_task_draw_amd:
case nir_intrinsic_load_ring_task_payload_amd: case nir_intrinsic_load_ring_task_payload_amd:
case nir_intrinsic_load_sample_positions_amd:
case nir_intrinsic_load_task_ring_entry_amd: case nir_intrinsic_load_task_ring_entry_amd:
case nir_intrinsic_load_task_ib_addr: case nir_intrinsic_load_task_ib_addr:
case nir_intrinsic_load_task_ib_stride: case nir_intrinsic_load_task_ib_stride:

3
src/compiler/nir/nir_intrinsics.py
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@@ -1303,6 +1303,9 @@ store("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET, WRIT
# Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0} # Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0}
intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE])
# src[] = { sample_id }
intrinsic("load_sample_positions_amd", src_comp=[1], dest_comp=2, flags=[CAN_ELIMINATE, CAN_REORDER])
# Descriptor where TCS outputs are stored for TES # Descriptor where TCS outputs are stored for TES
system_value("ring_tess_offchip_amd", 4) system_value("ring_tess_offchip_amd", 4)
system_value("ring_tess_offchip_offset_amd", 1) system_value("ring_tess_offchip_offset_amd", 1)