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radv: use next_stage for determining the stage to lower NGG

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If the next stage is FS, it's also the last VGT API stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24273>
This commit is contained in:
Samuel Pitoiset
2023-07-20 17:31:55 +02:00
committed by Marge Bot
parent 340f74e468
commit 7f173d1ff3
5 changed files with 7 additions and 9 deletions
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7
src/amd/vulkan/radv_pipeline.c
View File

@@ -503,8 +503,7 @@ non_uniform_access_callback(const nir_src *src, void *_)
void
radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout,
const struct radv_pipeline_key *pipeline_key, unsigned last_vgt_api_stage,
struct radv_pipeline_stage *stage)
const struct radv_pipeline_key *pipeline_key, struct radv_pipeline_stage *stage)
{
enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
bool progress;
@@ -628,10 +627,10 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
/* Lower I/O intrinsics to memory instructions. */
bool io_to_mem = radv_nir_lower_io_to_mem(device, stage);
bool lowered_ngg = stage->info.is_ngg && stage->stage == last_vgt_api_stage;
bool lowered_ngg = stage->info.is_ngg && stage->info.next_stage == MESA_SHADER_FRAGMENT;
if (lowered_ngg) {
radv_lower_ngg(device, stage, pipeline_key);
} else if (stage->stage == last_vgt_api_stage) {
} else if (stage->info.next_stage == MESA_SHADER_FRAGMENT) {
if (stage->stage != MESA_SHADER_GEOMETRY) {
NIR_PASS_V(stage->nir, ac_nir_lower_legacy_vs, gfx_level,
stage->info.outinfo.clip_dist_mask | stage->info.outinfo.cull_dist_mask,

2
src/amd/vulkan/radv_pipeline_compute.c
View File

@@ -161,7 +161,7 @@ radv_compile_cs(struct radv_device *device, struct vk_pipeline_cache *cache, str
cs_stage->info.inline_push_constant_mask = cs_stage->args.ac.inline_push_const_mask;
/* Postprocess NIR. */
radv_postprocess_nir(device, pipeline_layout, pipeline_key, MESA_SHADER_NONE, cs_stage);
radv_postprocess_nir(device, pipeline_layout, pipeline_key, cs_stage);
if (radv_can_dump_shader(device, cs_stage->nir, false))
nir_print_shader(cs_stage->nir, stderr);

2
src/amd/vulkan/radv_pipeline_graphics.c
View File

@@ -2655,7 +2655,7 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk
{
int64_t stage_start = os_time_get_nano();
radv_postprocess_nir(device, pipeline_layout, pipeline_key, pipeline->last_vgt_api_stage, &stages[i]);
radv_postprocess_nir(device, pipeline_layout, pipeline_key, &stages[i]);
stages[i].feedback.duration += os_time_get_nano() - stage_start;

2
src/amd/vulkan/radv_pipeline_rt.c
View File

@@ -391,7 +391,7 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
temp_stage.nir = shaders[i];
radv_nir_lower_rt_abi(temp_stage.nir, pCreateInfo, &temp_stage.args, &stage->info, stack_size, i > 0);
radv_optimize_nir(temp_stage.nir, pipeline_key->optimisations_disabled);
radv_postprocess_nir(device, pipeline_layout, pipeline_key, MESA_SHADER_NONE, &temp_stage);
radv_postprocess_nir(device, pipeline_layout, pipeline_key, &temp_stage);
if (radv_can_dump_shader(device, temp_stage.nir, false))
nir_print_shader(temp_stage.nir, stderr);

3
src/amd/vulkan/radv_shader.h
View File

@@ -603,8 +603,7 @@ void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
void radv_optimize_nir_algebraic(nir_shader *shader, bool opt_offsets);
void radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout,
const struct radv_pipeline_key *pipeline_key, unsigned last_vgt_api_stage,
struct radv_pipeline_stage *stage);
const struct radv_pipeline_key *pipeline_key, struct radv_pipeline_stage *stage);
nir_shader *radv_parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreateInfo *sinfo,
const struct radv_pipeline_key *key);