radeonsi: implement two lds base load intrinsics

LDS will be accessed starting from esgs_ring which has offset 0.
So ngg_scratch and ngg_emit base address is just the offset from
the esgs_ring base.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17109>

src/gallium/drivers/radeonsi/si_shader_llvm.c

@@ -922,6 +922,12 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin
    case nir_intrinsic_load_ring_attr_amd:
       return si_llvm_build_attr_ring_desc(ctx);
 
+   case nir_intrinsic_load_lds_ngg_scratch_base_amd:
+      return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_scratch.value, ctx->ac.i32, "");
+
+   case nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd:
+      return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, ctx->ac.i32, "");
+
    default:
       return NULL;
    }