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ac/nir,radv: move force_persample to ac_shader_info::force_persample

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Avoid accessing radv-specific structures during the meat of NIR-to-LLVM
translation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
2017-06-25 19:36:06 +02:00
parent 25ff22e390
commit 7de445377c
6 changed files with 10 additions and 6 deletions
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4
src/amd/common/ac_nir_to_llvm.c
View File

@@ -4003,11 +4003,9 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
break;
case nir_intrinsic_load_sample_id:
ctx->nctx->shader_info->fs.force_persample = true;
result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
break;
case nir_intrinsic_load_sample_pos:
ctx->nctx->shader_info->fs.force_persample = true;
result = load_sample_pos(ctx->nctx);
break;
case nir_intrinsic_load_sample_mask_in:
@@ -4960,7 +4958,7 @@ handle_fs_input_decl(struct nir_to_llvm_context *ctx,
unsigned interp_type;
if (variable->data.sample) {
interp_type = INTERP_SAMPLE;
ctx->shader_info->fs.force_persample = true;
ctx->shader_info->info.ps.force_persample = true;
} else if (variable->data.centroid)
interp_type = INTERP_CENTROID;
else

1
src/amd/common/ac_nir_to_llvm.h
View File

@@ -169,7 +169,6 @@ struct ac_shader_variant_info {
bool writes_sample_mask;
bool early_fragment_test;
bool writes_memory;
bool force_persample;
bool prim_id_input;
bool layer_input;
} fs;

6
src/amd/common/ac_shader_info.c
View File

@@ -45,6 +45,12 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, struct ac_shader_info *info)
case nir_intrinsic_load_num_work_groups:
info->cs.grid_components_used = instr->num_components;
break;
case nir_intrinsic_load_sample_id:
info->ps.force_persample = true;
break;
case nir_intrinsic_load_sample_pos:
info->ps.force_persample = true;
break;
case nir_intrinsic_vulkan_resource_index:
info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
break;

1
src/amd/common/ac_shader_info.h
View File

@@ -36,6 +36,7 @@ struct ac_shader_info {
bool needs_instance_id;
} vs;
struct {
bool force_persample;
bool needs_sample_positions;
} ps;
struct {

2
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -836,7 +836,7 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
ps->config.spi_ps_input_addr);
if (ps->info.fs.force_persample)
if (ps->info.info.ps.force_persample)
spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,

2
src/amd/vulkan/radv_pipeline.c
View File

@@ -1351,7 +1351,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
if (vkms && vkms->sampleShadingEnable) {
ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
} else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
} else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
ps_iter_samples = ms->num_samples;
}