intel/fs: Combine adjacent memory barriers
This will avoid generating multiple identical fences in a row. For Gen11+ we have multiple types of fences (affecting different variable modes), but is still better to combine them in a single scoped barrier so that the translation to backend IR have the option of dispatching both fences in parallel. This will clean up redundant barriers from various dEQP-VK.memory_model.* tests. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
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Marge Bot

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7d54b84d49
@@ -824,6 +824,26 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
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}
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}
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static
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bool combine_all_barriers(nir_intrinsic_instr *a,
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nir_intrinsic_instr *b,
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void *data)
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{
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/* Translation to backend IR will get rid of modes we don't care about, so
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* no harm in always combining them.
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*
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* TODO: While HW has only ACQUIRE|RELEASE fences, we could improve the
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* scheduling so that it can take advantage of the different semantics.
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*/
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nir_intrinsic_set_memory_modes(a, nir_intrinsic_memory_modes(a) |
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nir_intrinsic_memory_modes(b));
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nir_intrinsic_set_memory_semantics(a, nir_intrinsic_memory_semantics(a) |
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nir_intrinsic_memory_semantics(b));
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nir_intrinsic_set_memory_scope(a, MAX2(nir_intrinsic_memory_scope(a),
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nir_intrinsic_memory_scope(b)));
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return true;
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}
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/* Prepare the given shader for codegen
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*
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* This function is intended to be called right before going into the actual
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@@ -843,6 +863,8 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
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OPT(brw_nir_lower_mem_access_bit_sizes, devinfo);
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OPT(nir_opt_combine_memory_barriers, combine_all_barriers, NULL);
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do {
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progress = false;
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OPT(nir_opt_algebraic_before_ffma);
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