Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
This commit is contained in:
Dave Airlie
@@ -39,224 +39,6 @@
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#include "swrast/swrast.h"
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static void
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intel_set_span_functions(struct intel_context *intel,
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struct gl_renderbuffer *rb);
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#define SPAN_CACHE_SIZE 4096
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static void
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get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
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{
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if (irb->span_cache == NULL) {
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irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
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irb->span_cache_offset = -1;
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}
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if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
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irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
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dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
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SPAN_CACHE_SIZE, irb->span_cache);
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}
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}
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static void
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clear_span_cache(struct intel_renderbuffer *irb)
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{
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irb->span_cache_offset = -1;
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}
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static uint32_t
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pread_32(struct intel_renderbuffer *irb, uint32_t offset)
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{
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get_span_cache(irb, offset);
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return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
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}
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static uint32_t
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pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
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{
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get_span_cache(irb, offset);
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return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
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0xff000000;
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}
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static uint16_t
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pread_16(struct intel_renderbuffer *irb, uint32_t offset)
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{
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get_span_cache(irb, offset);
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return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
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}
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static uint8_t
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pread_8(struct intel_renderbuffer *irb, uint32_t offset)
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{
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get_span_cache(irb, offset);
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return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
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}
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static void
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pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
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{
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clear_span_cache(irb);
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dri_bo_subdata(irb->region->buffer, offset, 4, &val);
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}
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static void
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pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
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{
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clear_span_cache(irb);
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dri_bo_subdata(irb->region->buffer, offset, 3, &val);
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}
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static void
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pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
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{
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clear_span_cache(irb);
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dri_bo_subdata(irb->region->buffer, offset, 2, &val);
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}
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static void
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pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
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{
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clear_span_cache(irb);
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dri_bo_subdata(irb->region->buffer, offset, 1, &val);
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}
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static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
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struct intel_context *intel,
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int x, int y)
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{
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x += intel->drawX;
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y += intel->drawY;
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return (y * irb->region->pitch + x) * irb->region->cpp;
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}
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/*
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* Deal with tiled surfaces
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*/
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static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
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struct intel_context *intel,
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int x, int y)
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{
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int tile_stride;
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int xbyte;
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int x_tile_off, y_tile_off;
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int x_tile_number, y_tile_number;
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int tile_off, tile_base;
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tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
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x += intel->drawX;
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y += intel->drawY;
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xbyte = x * irb->region->cpp;
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x_tile_off = xbyte & 0x1ff;
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y_tile_off = y & 7;
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x_tile_number = xbyte >> 9;
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y_tile_number = y >> 3;
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tile_off = (y_tile_off << 9) + x_tile_off;
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switch (irb->region->bit_6_swizzle) {
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case I915_BIT_6_SWIZZLE_NONE:
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break;
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case I915_BIT_6_SWIZZLE_9:
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tile_off ^= ((tile_off >> 3) & 64);
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break;
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case I915_BIT_6_SWIZZLE_9_10:
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tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
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break;
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case I915_BIT_6_SWIZZLE_9_11:
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tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
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break;
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case I915_BIT_6_SWIZZLE_9_10_11:
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tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
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((tile_off >> 5) & 64);
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break;
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default:
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fprintf(stderr, "Unknown tile swizzling mode %d\n",
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irb->region->bit_6_swizzle);
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exit(1);
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}
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tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
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#if 0
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printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
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x, y, tile_off, tile_base,
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tile_off + tile_base,
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irb->pfPitch, tile_stride);
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#endif
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return tile_base + tile_off;
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}
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static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
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struct intel_context *intel,
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int x, int y)
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{
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int tile_stride;
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int xbyte;
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int x_tile_off, y_tile_off;
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int x_tile_number, y_tile_number;
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int tile_off, tile_base;
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tile_stride = (irb->pfPitch * irb->region->cpp) << 5;
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x += intel->drawX;
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y += intel->drawY;
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xbyte = x * irb->region->cpp;
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x_tile_off = xbyte & 0x7f;
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y_tile_off = y & 0x1f;
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x_tile_number = xbyte >> 7;
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y_tile_number = y >> 5;
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tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
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(x_tile_off & 0xf);
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switch (irb->region->bit_6_swizzle) {
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case I915_BIT_6_SWIZZLE_NONE:
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break;
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case I915_BIT_6_SWIZZLE_9:
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tile_off ^= ((tile_off >> 3) & 64);
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break;
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case I915_BIT_6_SWIZZLE_9_10:
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tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
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break;
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case I915_BIT_6_SWIZZLE_9_11:
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tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
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break;
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case I915_BIT_6_SWIZZLE_9_10_11:
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tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
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((tile_off >> 5) & 64);
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break;
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default:
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fprintf(stderr, "Unknown tile swizzling mode %d\n",
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irb->region->bit_6_swizzle);
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exit(1);
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}
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tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
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return tile_base + tile_off;
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}
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/*
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break intelWriteRGBASpan_ARGB8888
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*/
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@@ -269,7 +51,10 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
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struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
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const GLint yScale = irb->RenderToTexture ? 1 : -1; \
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const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
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GLubyte *buf = (GLubyte *) irb->pfMap \
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+ (intel->drawY * irb->pfPitch + intel->drawX) * irb->region->cpp;\
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GLuint p; \
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assert(irb->pfMap);\
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(void) p;
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/* XXX FBO: this is identical to the macro in spantmp2.h except we get
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@@ -284,14 +69,12 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
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int miny = intel->pClipRects[_nc].y1 - intel->drawY; \
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int maxx = intel->pClipRects[_nc].x2 - intel->drawX; \
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int maxy = intel->pClipRects[_nc].y2 - intel->drawY;
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#if 0
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}}
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#endif
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#define Y_FLIP(_y) ((_y) * yScale + yBias)
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/* XXX with GEM, these need to tell the kernel */
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#define HW_LOCK()
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#define HW_UNLOCK()
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@@ -303,8 +86,7 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
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#define TAG(x) intel##x##_RGB565
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#define TAG2(x,y) intel##x##_RGB565##y
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#define GET_VALUE(X, Y) pread_16(irb, no_tile_swizzle(irb, intel, X, Y))
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#define PUT_VALUE(X, Y, V) pwrite_16(irb, no_tile_swizzle(irb, intel, X, Y), V)
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#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 2)
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#include "spantmp2.h"
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/* 32 bit, ARGB8888 color spanline and pixel functions
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@@ -314,89 +96,17 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
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#define TAG(x) intel##x##_ARGB8888
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#define TAG2(x,y) intel##x##_ARGB8888##y
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#define GET_VALUE(X, Y) pread_32(irb, no_tile_swizzle(irb, intel, X, Y))
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#define PUT_VALUE(X, Y, V) pwrite_32(irb, no_tile_swizzle(irb, intel, X, Y), V)
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#include "spantmp2.h"
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/* 32 bit, xRGB8888 color spanline and pixel functions
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*/
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#define SPANTMP_PIXEL_FMT GL_BGRA
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
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#define TAG(x) intel##x##_xRGB8888
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#define TAG2(x,y) intel##x##_xRGB8888##y
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#define GET_VALUE(X, Y) pread_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y))
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#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y), V)
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#include "spantmp2.h"
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/* 16 bit RGB565 color tile spanline and pixel functions
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*/
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#define SPANTMP_PIXEL_FMT GL_RGB
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
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#define TAG(x) intel_XTile_##x##_RGB565
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#define TAG2(x,y) intel_XTile_##x##_RGB565##y
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#define GET_VALUE(X, Y) pread_16(irb, x_tile_swizzle(irb, intel, X, Y))
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#define PUT_VALUE(X, Y, V) pwrite_16(irb, x_tile_swizzle(irb, intel, X, Y), V)
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#include "spantmp2.h"
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#define SPANTMP_PIXEL_FMT GL_RGB
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
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#define TAG(x) intel_YTile_##x##_RGB565
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#define TAG2(x,y) intel_YTile_##x##_RGB565##y
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#define GET_VALUE(X, Y) pread_16(irb, y_tile_swizzle(irb, intel, X, Y))
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#define PUT_VALUE(X, Y, V) pwrite_16(irb, y_tile_swizzle(irb, intel, X, Y), V)
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#include "spantmp2.h"
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/* 32 bit ARGB888 color tile spanline and pixel functions
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*/
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#define SPANTMP_PIXEL_FMT GL_BGRA
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
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#define TAG(x) intel_XTile_##x##_ARGB8888
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#define TAG2(x,y) intel_XTile_##x##_ARGB8888##y
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#define GET_VALUE(X, Y) pread_32(irb, x_tile_swizzle(irb, intel, X, Y))
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#define PUT_VALUE(X, Y, V) pwrite_32(irb, x_tile_swizzle(irb, intel, X, Y), V)
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#include "spantmp2.h"
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#define SPANTMP_PIXEL_FMT GL_BGRA
|
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
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#define TAG(x) intel_YTile_##x##_ARGB8888
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#define TAG2(x,y) intel_YTile_##x##_ARGB8888##y
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#define GET_VALUE(X, Y) pread_32(irb, y_tile_swizzle(irb, intel, X, Y))
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#define PUT_VALUE(X, Y, V) pwrite_32(irb, y_tile_swizzle(irb, intel, X, Y), V)
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#include "spantmp2.h"
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/* 32 bit xRGB888 color tile spanline and pixel functions
|
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*/
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#define SPANTMP_PIXEL_FMT GL_BGRA
|
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
|
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#define TAG(x) intel_XTile_##x##_xRGB8888
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#define TAG2(x,y) intel_XTile_##x##_xRGB8888##y
|
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#define GET_VALUE(X, Y) pread_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y))
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#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y), V)
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#include "spantmp2.h"
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#define SPANTMP_PIXEL_FMT GL_BGRA
|
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
|
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|
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#define TAG(x) intel_YTile_##x##_xRGB8888
|
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#define TAG2(x,y) intel_YTile_##x##_xRGB8888##y
|
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#define GET_VALUE(X, Y) pread_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y))
|
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#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y), V)
|
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#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 4)
|
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#include "spantmp2.h"
|
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|
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#define LOCAL_DEPTH_VARS \
|
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struct intel_context *intel = intel_context(ctx); \
|
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struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
|
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const GLuint pitch = irb->pfPitch/***XXX region->pitch*/; /* in pixels */ \
|
||||
const GLint yScale = irb->RenderToTexture ? 1 : -1; \
|
||||
const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1;
|
||||
const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
|
||||
char *buf = (char *) irb->pfMap/*XXX use region->map*/ + \
|
||||
(intel->drawY * pitch + intel->drawX) * irb->region->cpp;
|
||||
|
||||
|
||||
#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
|
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@@ -405,37 +115,18 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
|
||||
** 16-bit depthbuffer functions.
|
||||
**/
|
||||
#define VALUE_TYPE GLushort
|
||||
#define WRITE_DEPTH(_x, _y, d) \
|
||||
pwrite_16(irb, no_tile_swizzle(irb, intel, _x, _y), d)
|
||||
#define READ_DEPTH(d, _x, _y) \
|
||||
d = pread_16(irb, no_tile_swizzle(irb, intel, _x, _y))
|
||||
|
||||
#define WRITE_DEPTH( _x, _y, d ) \
|
||||
((GLushort *)buf)[(_x) + (_y) * pitch] = d;
|
||||
|
||||
#define READ_DEPTH( d, _x, _y ) \
|
||||
d = ((GLushort *)buf)[(_x) + (_y) * pitch];
|
||||
|
||||
|
||||
#define TAG(x) intel##x##_z16
|
||||
#include "depthtmp.h"
|
||||
|
||||
|
||||
/**
|
||||
** 16-bit x tile depthbuffer functions.
|
||||
**/
|
||||
#define VALUE_TYPE GLushort
|
||||
#define WRITE_DEPTH(_x, _y, d) \
|
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pwrite_16(irb, x_tile_swizzle(irb, intel, _x, _y), d)
|
||||
#define READ_DEPTH(d, _x, _y) \
|
||||
d = pread_16(irb, x_tile_swizzle(irb, intel, _x, _y))
|
||||
#define TAG(x) intel_XTile_##x##_z16
|
||||
#include "depthtmp.h"
|
||||
|
||||
/**
|
||||
** 16-bit y tile depthbuffer functions.
|
||||
**/
|
||||
#define VALUE_TYPE GLushort
|
||||
#define WRITE_DEPTH(_x, _y, d) \
|
||||
pwrite_16(irb, y_tile_swizzle(irb, intel, _x, _y), d)
|
||||
#define READ_DEPTH(d, _x, _y) \
|
||||
d = pread_16(irb, y_tile_swizzle(irb, intel, _x, _y))
|
||||
#define TAG(x) intel_YTile_##x##_z16
|
||||
#include "depthtmp.h"
|
||||
|
||||
|
||||
/**
|
||||
** 24/8-bit interleaved depth/stencil functions
|
||||
** Note: we're actually reading back combined depth+stencil values.
|
||||
@@ -445,13 +136,14 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
|
||||
#define VALUE_TYPE GLuint
|
||||
|
||||
/* Change ZZZS -> SZZZ */
|
||||
#define WRITE_DEPTH(_x, _y, d) \
|
||||
pwrite_32(irb, no_tile_swizzle(irb, intel, _x, _y), \
|
||||
((d) >> 8) | ((d) << 24))
|
||||
#define WRITE_DEPTH( _x, _y, d ) { \
|
||||
GLuint tmp = ((d) >> 8) | ((d) << 24); \
|
||||
((GLuint *)buf)[(_x) + (_y) * pitch] = tmp; \
|
||||
}
|
||||
|
||||
/* Change SZZZ -> ZZZS */
|
||||
#define READ_DEPTH( d, _x, _y ) { \
|
||||
GLuint tmp = pread_32(irb, no_tile_swizzle(irb, intel, _x, _y)); \
|
||||
GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch]; \
|
||||
d = (tmp << 8) | (tmp >> 24); \
|
||||
}
|
||||
|
||||
@@ -459,115 +151,23 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
|
||||
#include "depthtmp.h"
|
||||
|
||||
|
||||
/**
|
||||
** 24/8-bit x-tile interleaved depth/stencil functions
|
||||
** Note: we're actually reading back combined depth+stencil values.
|
||||
** The wrappers in main/depthstencil.c are used to extract the depth
|
||||
** and stencil values.
|
||||
**/
|
||||
#define VALUE_TYPE GLuint
|
||||
|
||||
/* Change ZZZS -> SZZZ */
|
||||
#define WRITE_DEPTH(_x, _y, d) \
|
||||
pwrite_32(irb, x_tile_swizzle(irb, intel, _x, _y), \
|
||||
((d) >> 8) | ((d) << 24)) \
|
||||
|
||||
/* Change SZZZ -> ZZZS */
|
||||
#define READ_DEPTH( d, _x, _y ) { \
|
||||
GLuint tmp = pread_32(irb, x_tile_swizzle(irb, intel, _x, _y)); \
|
||||
d = (tmp << 8) | (tmp >> 24); \
|
||||
}
|
||||
|
||||
#define TAG(x) intel_XTile_##x##_z24_s8
|
||||
#include "depthtmp.h"
|
||||
|
||||
/**
|
||||
** 24/8-bit y-tile interleaved depth/stencil functions
|
||||
** Note: we're actually reading back combined depth+stencil values.
|
||||
** The wrappers in main/depthstencil.c are used to extract the depth
|
||||
** and stencil values.
|
||||
**/
|
||||
#define VALUE_TYPE GLuint
|
||||
|
||||
/* Change ZZZS -> SZZZ */
|
||||
#define WRITE_DEPTH(_x, _y, d) \
|
||||
pwrite_32(irb, y_tile_swizzle(irb, intel, _x, _y), \
|
||||
((d) >> 8) | ((d) << 24))
|
||||
|
||||
/* Change SZZZ -> ZZZS */
|
||||
#define READ_DEPTH( d, _x, _y ) { \
|
||||
GLuint tmp = pread_32(irb, y_tile_swizzle(irb, intel, _x, _y)); \
|
||||
d = (tmp << 8) | (tmp >> 24); \
|
||||
}
|
||||
|
||||
#define TAG(x) intel_YTile_##x##_z24_s8
|
||||
#include "depthtmp.h"
|
||||
|
||||
|
||||
/**
|
||||
** 8-bit stencil function (XXX FBO: This is obsolete)
|
||||
**/
|
||||
#define WRITE_STENCIL(_x, _y, d) \
|
||||
pwrite_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3, d)
|
||||
#define WRITE_STENCIL( _x, _y, d ) { \
|
||||
GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch]; \
|
||||
tmp &= 0xffffff; \
|
||||
tmp |= ((d) << 24); \
|
||||
((GLuint *) buf)[(_x) + (_y) * pitch] = tmp; \
|
||||
}
|
||||
|
||||
#define READ_STENCIL(d, _x, _y) \
|
||||
d = pread_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3);
|
||||
#define READ_STENCIL( d, _x, _y ) \
|
||||
d = ((GLuint *)buf)[(_x) + (_y) * pitch] >> 24;
|
||||
|
||||
#define TAG(x) intel##x##_z24_s8
|
||||
#include "stenciltmp.h"
|
||||
|
||||
/**
|
||||
** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
|
||||
**/
|
||||
#define WRITE_STENCIL(_x, _y, d) \
|
||||
pwrite_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3, d)
|
||||
|
||||
#define READ_STENCIL(d, _x, _y) \
|
||||
d = pread_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3);
|
||||
|
||||
#define TAG(x) intel_XTile_##x##_z24_s8
|
||||
#include "stenciltmp.h"
|
||||
|
||||
/**
|
||||
** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
|
||||
**/
|
||||
#define WRITE_STENCIL(_x, _y, d) \
|
||||
pwrite_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3, d)
|
||||
|
||||
#define READ_STENCIL(d, _x, _y) \
|
||||
d = pread_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3)
|
||||
|
||||
#define TAG(x) intel_YTile_##x##_z24_s8
|
||||
#include "stenciltmp.h"
|
||||
|
||||
void
|
||||
intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
|
||||
{
|
||||
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
|
||||
|
||||
if (irb == NULL || irb->region == NULL)
|
||||
return;
|
||||
|
||||
irb->pfPitch = irb->region->pitch;
|
||||
|
||||
intel_set_span_functions(intel, rb);
|
||||
}
|
||||
|
||||
void
|
||||
intel_renderbuffer_unmap(struct intel_context *intel,
|
||||
struct gl_renderbuffer *rb)
|
||||
{
|
||||
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
|
||||
|
||||
if (irb == NULL || irb->region == NULL)
|
||||
return;
|
||||
|
||||
clear_span_cache(irb);
|
||||
irb->pfPitch = 0;
|
||||
|
||||
rb->GetRow = NULL;
|
||||
rb->PutRow = NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* Map or unmap all the renderbuffers which we may need during
|
||||
@@ -586,13 +186,23 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
|
||||
{
|
||||
GLcontext *ctx = &intel->ctx;
|
||||
GLuint i, j;
|
||||
struct intel_renderbuffer *irb;
|
||||
|
||||
/* color draw buffers */
|
||||
for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
|
||||
if (map)
|
||||
intel_renderbuffer_map(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
|
||||
else
|
||||
intel_renderbuffer_unmap(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
|
||||
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[j];
|
||||
irb = intel_renderbuffer(rb);
|
||||
if (irb) {
|
||||
/* this is a user-created intel_renderbuffer */
|
||||
if (irb->region) {
|
||||
if (map)
|
||||
intel_region_map(intel, irb->region);
|
||||
else
|
||||
intel_region_unmap(intel, irb->region);
|
||||
irb->pfMap = irb->region->map;
|
||||
irb->pfPitch = irb->region->pitch;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* check for render to textures */
|
||||
@@ -615,28 +225,77 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
|
||||
}
|
||||
|
||||
/* color read buffers */
|
||||
if (map)
|
||||
intel_renderbuffer_map(intel, ctx->ReadBuffer->_ColorReadBuffer);
|
||||
else
|
||||
intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer);
|
||||
irb = intel_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
|
||||
if (irb && irb->region) {
|
||||
if (map)
|
||||
intel_region_map(intel, irb->region);
|
||||
else
|
||||
intel_region_unmap(intel, irb->region);
|
||||
irb->pfMap = irb->region->map;
|
||||
irb->pfPitch = irb->region->pitch;
|
||||
}
|
||||
|
||||
/* Account for front/back color page flipping.
|
||||
* The span routines use the pfMap and pfPitch fields which will
|
||||
* swap the front/back region map/pitch if we're page flipped.
|
||||
* Do this after mapping, above, so the map field is valid.
|
||||
*/
|
||||
#if 0
|
||||
if (map && ctx->DrawBuffer->Name == 0) {
|
||||
struct intel_renderbuffer *irbFront
|
||||
= intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_FRONT_LEFT);
|
||||
struct intel_renderbuffer *irbBack
|
||||
= intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_BACK_LEFT);
|
||||
if (irbBack) {
|
||||
/* double buffered */
|
||||
if (intel->sarea->pf_current_page == 0) {
|
||||
irbFront->pfMap = irbFront->region->map;
|
||||
irbFront->pfPitch = irbFront->region->pitch;
|
||||
irbBack->pfMap = irbBack->region->map;
|
||||
irbBack->pfPitch = irbBack->region->pitch;
|
||||
}
|
||||
else {
|
||||
irbFront->pfMap = irbBack->region->map;
|
||||
irbFront->pfPitch = irbBack->region->pitch;
|
||||
irbBack->pfMap = irbFront->region->map;
|
||||
irbBack->pfPitch = irbFront->region->pitch;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* depth buffer (Note wrapper!) */
|
||||
if (ctx->DrawBuffer->_DepthBuffer) {
|
||||
if (map)
|
||||
intel_renderbuffer_map(intel, ctx->DrawBuffer->_DepthBuffer->Wrapped);
|
||||
else
|
||||
intel_renderbuffer_unmap(intel,
|
||||
ctx->DrawBuffer->_DepthBuffer->Wrapped);
|
||||
irb = intel_renderbuffer(ctx->DrawBuffer->_DepthBuffer->Wrapped);
|
||||
if (irb && irb->region) {
|
||||
if (map) {
|
||||
intel_region_map(intel, irb->region);
|
||||
irb->pfMap = irb->region->map;
|
||||
irb->pfPitch = irb->region->pitch;
|
||||
}
|
||||
else {
|
||||
intel_region_unmap(intel, irb->region);
|
||||
irb->pfMap = irb->region->map;
|
||||
irb->pfPitch = irb->region->pitch;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* stencil buffer (Note wrapper!) */
|
||||
if (ctx->DrawBuffer->_StencilBuffer) {
|
||||
if (map)
|
||||
intel_renderbuffer_map(intel,
|
||||
ctx->DrawBuffer->_StencilBuffer->Wrapped);
|
||||
else
|
||||
intel_renderbuffer_unmap(intel,
|
||||
ctx->DrawBuffer->_StencilBuffer->Wrapped);
|
||||
irb = intel_renderbuffer(ctx->DrawBuffer->_StencilBuffer->Wrapped);
|
||||
if (irb && irb->region) {
|
||||
if (map) {
|
||||
intel_region_map(intel, irb->region);
|
||||
irb->pfMap = irb->region->map;
|
||||
irb->pfPitch = irb->region->pitch;
|
||||
}
|
||||
else {
|
||||
intel_region_unmap(intel, irb->region);
|
||||
irb->pfMap = irb->region->map;
|
||||
irb->pfPitch = irb->region->pitch;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -654,9 +313,18 @@ intelSpanRenderStart(GLcontext * ctx)
|
||||
struct intel_context *intel = intel_context(ctx);
|
||||
GLuint i;
|
||||
|
||||
intelFlush(&intel->ctx);
|
||||
intelFinish(&intel->ctx);
|
||||
LOCK_HARDWARE(intel);
|
||||
|
||||
#if 0
|
||||
/* Just map the framebuffer and all textures. Bufmgr code will
|
||||
* take care of waiting on the necessary fences:
|
||||
*/
|
||||
intel_region_map(intel, intel->front_region);
|
||||
intel_region_map(intel, intel->back_region);
|
||||
intel_region_map(intel, intel->depth_region);
|
||||
#endif
|
||||
|
||||
for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
|
||||
if (ctx->Texture.Unit[i]._ReallyEnabled) {
|
||||
struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
|
||||
@@ -679,6 +347,14 @@ intelSpanRenderFinish(GLcontext * ctx)
|
||||
|
||||
_swrast_flush(ctx);
|
||||
|
||||
/* Now unmap the framebuffer:
|
||||
*/
|
||||
#if 0
|
||||
intel_region_unmap(intel, intel->front_region);
|
||||
intel_region_unmap(intel, intel->back_region);
|
||||
intel_region_unmap(intel, intel->depth_region);
|
||||
#endif
|
||||
|
||||
for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
|
||||
if (ctx->Texture.Unit[i]._ReallyEnabled) {
|
||||
struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
|
||||
@@ -705,108 +381,26 @@ intelInitSpanFuncs(GLcontext * ctx)
|
||||
* Plug in appropriate span read/write functions for the given renderbuffer.
|
||||
* These are used for the software fallbacks.
|
||||
*/
|
||||
static void
|
||||
intel_set_span_functions(struct intel_context *intel,
|
||||
struct gl_renderbuffer *rb)
|
||||
void
|
||||
intel_set_span_functions(struct gl_renderbuffer *rb)
|
||||
{
|
||||
struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
|
||||
uint32_t tiling;
|
||||
|
||||
/* If in GEM mode, we need to do the tile address swizzling ourselves,
|
||||
* instead of the fence registers handling it.
|
||||
*/
|
||||
if (intel->ttm)
|
||||
tiling = irb->region->tiling;
|
||||
else
|
||||
tiling = I915_TILING_NONE;
|
||||
|
||||
if (rb->_ActualFormat == GL_RGB5) {
|
||||
/* 565 RGB */
|
||||
switch (tiling) {
|
||||
case I915_TILING_NONE:
|
||||
default:
|
||||
intelInitPointers_RGB565(rb);
|
||||
break;
|
||||
case I915_TILING_X:
|
||||
intel_XTile_InitPointers_RGB565(rb);
|
||||
break;
|
||||
case I915_TILING_Y:
|
||||
intel_YTile_InitPointers_RGB565(rb);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (rb->_ActualFormat == GL_RGB8) {
|
||||
/* 8888 RGBx */
|
||||
switch (tiling) {
|
||||
case I915_TILING_NONE:
|
||||
default:
|
||||
intelInitPointers_xRGB8888(rb);
|
||||
break;
|
||||
case I915_TILING_X:
|
||||
intel_XTile_InitPointers_xRGB8888(rb);
|
||||
break;
|
||||
case I915_TILING_Y:
|
||||
intel_YTile_InitPointers_xRGB8888(rb);
|
||||
break;
|
||||
}
|
||||
intelInitPointers_RGB565(rb);
|
||||
}
|
||||
else if (rb->_ActualFormat == GL_RGBA8) {
|
||||
/* 8888 RGBA */
|
||||
switch (tiling) {
|
||||
case I915_TILING_NONE:
|
||||
default:
|
||||
intelInitPointers_ARGB8888(rb);
|
||||
break;
|
||||
case I915_TILING_X:
|
||||
intel_XTile_InitPointers_ARGB8888(rb);
|
||||
break;
|
||||
case I915_TILING_Y:
|
||||
intel_YTile_InitPointers_ARGB8888(rb);
|
||||
break;
|
||||
}
|
||||
intelInitPointers_ARGB8888(rb);
|
||||
}
|
||||
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
|
||||
switch (tiling) {
|
||||
case I915_TILING_NONE:
|
||||
default:
|
||||
intelInitDepthPointers_z16(rb);
|
||||
break;
|
||||
case I915_TILING_X:
|
||||
intel_XTile_InitDepthPointers_z16(rb);
|
||||
break;
|
||||
case I915_TILING_Y:
|
||||
intel_YTile_InitDepthPointers_z16(rb);
|
||||
break;
|
||||
}
|
||||
intelInitDepthPointers_z16(rb);
|
||||
}
|
||||
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 || /* XXX FBO remove */
|
||||
rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
|
||||
switch (tiling) {
|
||||
case I915_TILING_NONE:
|
||||
default:
|
||||
intelInitDepthPointers_z24_s8(rb);
|
||||
break;
|
||||
case I915_TILING_X:
|
||||
intel_XTile_InitDepthPointers_z24_s8(rb);
|
||||
break;
|
||||
case I915_TILING_Y:
|
||||
intel_YTile_InitDepthPointers_z24_s8(rb);
|
||||
break;
|
||||
}
|
||||
intelInitDepthPointers_z24_s8(rb);
|
||||
}
|
||||
else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
|
||||
switch (tiling) {
|
||||
case I915_TILING_NONE:
|
||||
default:
|
||||
intelInitStencilPointers_z24_s8(rb);
|
||||
break;
|
||||
case I915_TILING_X:
|
||||
intel_XTile_InitStencilPointers_z24_s8(rb);
|
||||
break;
|
||||
case I915_TILING_Y:
|
||||
intel_YTile_InitStencilPointers_z24_s8(rb);
|
||||
break;
|
||||
}
|
||||
else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) { /* XXX FBO remove */
|
||||
intelInitStencilPointers_z24_s8(rb);
|
||||
}
|
||||
else {
|
||||
_mesa_problem(NULL,
|
||||
|
||||
Reference in New Issue
Block a user