Reduce the size of mesa's internal fragment and vertex program
representations by switching to packed structures for registers and instructions.
This commit is contained in:
@@ -130,7 +130,7 @@ static GLuint src_vector( struct i915_fragment_program *p,
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case PROGRAM_STATE_VAR:
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case PROGRAM_NAMED_PARAM:
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src = i915_emit_param4fv(
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p, program->Parameters->Parameters[source->Index].Values );
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p, program->Parameters->ParameterValues[source->Index] );
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break;
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default:
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@@ -139,10 +139,10 @@ static GLuint src_vector( struct i915_fragment_program *p,
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}
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src = swizzle(src,
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source->Swizzle[0],
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source->Swizzle[1],
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source->Swizzle[2],
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source->Swizzle[3]);
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GET_SWZ(source->Swizzle, 0),
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GET_SWZ(source->Swizzle, 1),
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GET_SWZ(source->Swizzle, 2),
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GET_SWZ(source->Swizzle, 3));
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if (source->NegateBase)
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src = negate( src, 1,1,1,1 );
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@@ -179,30 +179,30 @@ static GLuint get_result_flags( const struct fp_instruction *inst )
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GLuint flags = 0;
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if (inst->Saturate) flags |= A0_DEST_SATURATE;
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if (inst->DstReg.WriteMask[0]) flags |= A0_DEST_CHANNEL_X;
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if (inst->DstReg.WriteMask[1]) flags |= A0_DEST_CHANNEL_Y;
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if (inst->DstReg.WriteMask[2]) flags |= A0_DEST_CHANNEL_Z;
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if (inst->DstReg.WriteMask[3]) flags |= A0_DEST_CHANNEL_W;
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if (inst->DstReg.WriteMask & WRITEMASK_X) flags |= A0_DEST_CHANNEL_X;
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if (inst->DstReg.WriteMask & WRITEMASK_Y) flags |= A0_DEST_CHANNEL_Y;
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if (inst->DstReg.WriteMask & WRITEMASK_Z) flags |= A0_DEST_CHANNEL_Z;
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if (inst->DstReg.WriteMask & WRITEMASK_W) flags |= A0_DEST_CHANNEL_W;
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return flags;
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}
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static GLuint translate_tex_src_bit( struct i915_fragment_program *p,
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static GLuint translate_tex_src_idx( struct i915_fragment_program *p,
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GLubyte bit )
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{
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switch (bit) {
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case TEXTURE_1D_BIT: return D0_SAMPLE_TYPE_2D;
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case TEXTURE_2D_BIT: return D0_SAMPLE_TYPE_2D;
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case TEXTURE_RECT_BIT: return D0_SAMPLE_TYPE_2D;
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case TEXTURE_3D_BIT: return D0_SAMPLE_TYPE_VOLUME;
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case TEXTURE_CUBE_BIT: return D0_SAMPLE_TYPE_CUBE;
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case TEXTURE_1D_INDEX: return D0_SAMPLE_TYPE_2D;
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case TEXTURE_2D_INDEX: return D0_SAMPLE_TYPE_2D;
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case TEXTURE_RECT_INDEX: return D0_SAMPLE_TYPE_2D;
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case TEXTURE_3D_INDEX: return D0_SAMPLE_TYPE_VOLUME;
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case TEXTURE_CUBE_INDEX: return D0_SAMPLE_TYPE_CUBE;
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default: i915_program_error(p, "TexSrcBit"); return 0;
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}
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}
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#define EMIT_TEX( OP ) \
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do { \
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GLuint dim = translate_tex_src_bit( p, inst->TexSrcBit ); \
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GLuint dim = translate_tex_src_idx( p, inst->TexSrcIdx ); \
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GLuint sampler = i915_emit_decl(p, REG_TYPE_S, \
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inst->TexSrcUnit, dim); \
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GLuint coord = src_vector( p, &inst->SrcReg[0], program); \
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@@ -592,10 +592,10 @@ static void upload_program( struct i915_fragment_program *p )
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swizzle(tmp, X,Y,X,Y),
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swizzle(tmp, X,X,ONE,ONE), 0);
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if (inst->DstReg.WriteMask[1]) {
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if (inst->DstReg.WriteMask & WRITEMASK_Y) {
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GLuint tmp1;
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if (inst->DstReg.WriteMask[0])
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if (inst->DstReg.WriteMask & WRITEMASK_X)
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tmp1 = i915_get_utemp( p );
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else
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tmp1 = tmp;
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@@ -614,7 +614,7 @@ static void upload_program( struct i915_fragment_program *p )
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i915_emit_const4fv( p, sin_constants ), 0);
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}
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if (inst->DstReg.WriteMask[0]) {
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if (inst->DstReg.WriteMask & WRITEMASK_X) {
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i915_emit_arith( p,
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A0_MUL,
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tmp, A0_DEST_CHANNEL_XYZ, 0,
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