intel/fs: Add support for atomic_fadd

Rework:
- Enable float32 atomic add with LSC (Sagar)
- disassemble new opcode (Caio)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>

src/intel/compiler/brw_disasm.c

@@ -487,10 +487,11 @@ static const char *const aop[16] = {
    [BRW_AOP_PREDEC] = "predec",
 };
 
-static const char *const aop_float[4] = {
+static const char *const aop_float[5] = {
    [BRW_AOP_FMAX]   = "fmax",
    [BRW_AOP_FMIN]   = "fmin",
    [BRW_AOP_FCMPWR] = "fcmpwr",
+   [BRW_AOP_FADD]   = "fadd",
 };
 
 static const char * const pixel_interpolator_msg_types[4] = {

src/intel/compiler/brw_eu_defines.h

@@ -1568,6 +1568,7 @@ enum brw_message_target {
 #define BRW_AOP_FMAX                  1
 #define BRW_AOP_FMIN                  2
 #define BRW_AOP_FCMPWR                3
+#define BRW_AOP_FADD                  4
 
 #define BRW_MATH_FUNCTION_INV                              1
 #define BRW_MATH_FUNCTION_LOG                              2

src/intel/compiler/brw_fs.cpp

@@ -5963,6 +5963,8 @@ brw_atomic_op_to_lsc_fatomic_op(uint32_t aop)
       return LSC_OP_ATOMIC_FMIN;
    case BRW_AOP_FCMPWR:
       return LSC_OP_ATOMIC_FCMPXCHG;
+   case BRW_AOP_FADD:
+      return LSC_OP_ATOMIC_FADD;
    default:
       unreachable("Unsupported float atomic opcode");
    }

src/intel/compiler/brw_fs_nir.cpp

@@ -4826,6 +4826,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
    case nir_intrinsic_global_atomic_comp_swap:
       nir_emit_global_atomic(bld, brw_aop_for_nir_intrinsic(instr), instr);
       break;
+   case nir_intrinsic_global_atomic_fadd:
    case nir_intrinsic_global_atomic_fmin:
    case nir_intrinsic_global_atomic_fmax:
    case nir_intrinsic_global_atomic_fcomp_swap:
@@ -4993,6 +4994,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
    case nir_intrinsic_ssbo_atomic_comp_swap:
       nir_emit_ssbo_atomic(bld, brw_aop_for_nir_intrinsic(instr), instr);
       break;
+   case nir_intrinsic_ssbo_atomic_fadd:
    case nir_intrinsic_ssbo_atomic_fmin:
    case nir_intrinsic_ssbo_atomic_fmax:
    case nir_intrinsic_ssbo_atomic_fcomp_swap:

src/intel/compiler/brw_nir.c

@@ -1426,6 +1426,7 @@ brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic)
    AOP_CASE(fmin):         return BRW_AOP_FMIN;
    AOP_CASE(fmax):         return BRW_AOP_FMAX;
    AOP_CASE(fcomp_swap):   return BRW_AOP_FCMPWR;
+   AOP_CASE(fadd):         return BRW_AOP_FADD;
 
 #undef AOP_CASE