From 7aaa016b23d066b31c1aa432b2fac0b6e950eb03 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 24 Aug 2022 17:09:42 +0200 Subject: [PATCH] radv: stop setting CB_COLOR_CONTROL.ROP3 from the pipeline This is useless because logic op is a dynamic state and it's already emitted from the cmdbuf. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_pipeline.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index e153aaadc20..ddff5f6deb6 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -678,13 +678,6 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline, const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; int i; - if (state->cb) { - if (state->cb->logic_op_enable) - cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(state->cb->logic_op)); - else - cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY); - } - if (device->instance->debug_flags & RADV_DEBUG_NO_ATOC_DITHERING) { blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |