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spirv/nir: add support for AMD_shader_ballot and Groups capability

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This commit also renames existing AMD capabilities:
 - gcn_shader -> amd_gcn_shader
 - trinary_minmax -> amd_trinary_minmax

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
This commit is contained in:
Daniel Schürmann
2018-05-09 20:41:23 +02:00
committed by Connor Abbott
parent ea51275e07
commit 7a858f274c
6 changed files with 139 additions and 11 deletions
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5
src/amd/vulkan/radv_shader.c
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@@ -245,6 +245,9 @@ radv_shader_compile_to_nir(struct radv_device *device,
const struct spirv_to_nir_options spirv_options = {
.lower_ubo_ssbo_access_to_offsets = true,
.caps = {
.amd_gcn_shader = true,
.amd_shader_ballot = false,
.amd_trinary_minmax = true,
.derivative_group = true,
.descriptor_array_dynamic_indexing = true,
.descriptor_array_non_uniform_indexing = true,
@@ -253,7 +256,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
.draw_parameters = true,
.float16 = true,
.float64 = true,
.gcn_shader = true,
.geometry_streams = true,
.image_read_without_format = true,
.image_write_without_format = true,
@@ -277,7 +279,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
.subgroup_vote = true,
.tessellation = true,
.transform_feedback = true,
.trinary_minmax = true,
.variable_pointers = true,
},
.ubo_addr_format = nir_address_format_32bit_index_offset,