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radv: add support for MRTs compaction to avoid holes

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SPI_SHADER_COL_FORMAT allocates export memory and CB_SHADER_MASK
map them to higher MRTs if necessary. The hardware allows to remap
MRTs to avoid holes somehow.

For example, if we have a scenario where MRT0 is unused and only
MRT1 and MRT2 are used, SPI_SHADER_COL_FORMAT is 0x77 and
CB_SHADER_MASK/CB_TARGET_MASK are 0x770 (this assumes
SPI_SHADER_UINT16_ABGR is set).

This allows us to remove one workaround that was added for fixing
GPU hangs with DXVK. I think this is because SPI_SHADER_COL_FORMAT
expects contiguous MRTs to be allocated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5434>
This commit is contained in:
Samuel Pitoiset
2020-06-11 21:54:01 +02:00
committed by Marge Bot
parent 4e0dcbb880
commit 7a5e6fd25f
4 changed files with 41 additions and 43 deletions
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3
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -3586,8 +3586,7 @@ handle_fs_outputs_post(struct radv_shader_context *ctx)
values[j] = ac_to_float(&ctx->ac,
radv_load_output(ctx, i, j));
bool ret = si_export_mrt_color(ctx, values,
i - FRAG_RESULT_DATA0,
bool ret = si_export_mrt_color(ctx, values, index,
&color_args[index]);
if (ret)
index++;