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intel/gen12: Take into account opcode when decoding SWSB

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The interpretation of the fields is different depending whether the
instruction is a SEND/MATH or not.

This fixes the disassembly output for non-SEND/MATH instructions that
have both in-order and out-of-order dependencies.  Their dependencies
were wrongly represented as `@A $B` when the correct would be `@A
$B.dst`.

Fixes: 6154cdf924 ("intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.")
Fixes: 83612c0127 ("intel/disasm/gen12: Disassemble software scoreboard information.")
Acked-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
This commit is contained in:
Caio Marcelo de Oliveira Filho
2020-01-31 10:20:25 -08:00
parent bee5c9b0dc
commit 79788b8f7f
2 changed files with 7 additions and 3 deletions
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3
src/intel/compiler/brw_disasm.c
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@@ -1632,7 +1632,8 @@ qtr_ctrl(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst
static int
swsb(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
{
const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_swsb(devinfo, inst));
const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_opcode(devinfo, inst),
brw_inst_swsb(devinfo, inst));
if (swsb.regdist)
format(file, " @%d", swsb.regdist);
if (swsb.mode)