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isl: Enable volumetric STC_CCS,HiZ+CCS on gfx12.0

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The only remaining restriction applies to single sampled 3D textures on
Gen12.0. Move the check to disable CCS on such resources to the right
place.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28646>
This commit is contained in:
Rohan Garg
2024-04-23 14:58:22 +02:00
committed by Marge Bot
parent b69a34ab66
commit 7900ecdfc7
1 changed files with 6 additions and 6 deletions
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12
src/intel/isl/isl.c
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@@ -3077,12 +3077,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
return false;
if (ISL_GFX_VER(dev) >= 12) {
/* Wa_1406738321: 3D textures need a blit to a new surface in order to
* perform a resolve. For now, just disable CCS on TGL.
*/
if (dev->info->verx10 == 120 && surf->dim == ISL_SURF_DIM_3D)
return false;
if (isl_surf_usage_is_stencil(surf->usage)) {
/* HiZ and MCS aren't allowed with stencil */
assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
@@ -3140,6 +3134,12 @@ isl_surf_supports_ccs(const struct isl_device *dev,
} else {
/* Single-sampled color can't have MCS or HiZ */
assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
/* Wa_1406738321: 3D textures need a blit to a new surface
* in order to perform a resolve. For now, just disable CCS on TGL.
*/
if (dev->info->verx10 == 120 && surf->dim == ISL_SURF_DIM_3D)
return false;
}
/* On Gfx12, all CCS-compressed surface pitches must be multiples of