OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: update configuring occlusion query state on GFX12

Browse Source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
This commit is contained in:
Samuel Pitoiset
2024-05-27 14:12:31 +02:00
committed by Marge Bot
parent 61e78fb143
commit 78e272432b
1 changed files with 16 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -4859,8 +4859,6 @@ radv_flush_occlusion_query_state(struct radv_cmd_buffer *cmd_buffer)
if (!enable_occlusion_queries) { if (!enable_occlusion_queries) {
db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(gfx_level < GFX11); db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(gfx_level < GFX11);
} else { } else {
const uint32_t rasterization_samples = radv_get_rasterization_samples(cmd_buffer);
const uint32_t sample_rate = util_logbase2(rasterization_samples);
bool gfx10_perfect = bool gfx10_perfect =
gfx_level >= GFX10 && (cmd_buffer->state.perfect_occlusion_queries_enabled || gfx_level >= GFX10 && (cmd_buffer->state.perfect_occlusion_queries_enabled ||
cmd_buffer->state.inherited_query_control_flags & VK_QUERY_CONTROL_PRECISE_BIT); cmd_buffer->state.inherited_query_control_flags & VK_QUERY_CONTROL_PRECISE_BIT);
@@ -4870,15 +4868,27 @@ radv_flush_occlusion_query_state(struct radv_cmd_buffer *cmd_buffer)
* covered tiles, discards, and early depth testing. For more details, * covered tiles, discards, and early depth testing. For more details,
* see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */ * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) | db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) | S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) | S_028004_ZPASS_ENABLE(1) |
S_028004_SAMPLE_RATE(sample_rate) | S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1); S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
} else { } else {
db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) | S_028004_SAMPLE_RATE(sample_rate); db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1);
}
if (gfx_level < GFX12) {
const uint32_t rasterization_samples = radv_get_rasterization_samples(cmd_buffer);
const uint32_t sample_rate = util_logbase2(rasterization_samples);
db_count_control |= S_028004_SAMPLE_RATE(sample_rate);
} }
} }
radeon_opt_set_context_reg(cmd_buffer, R_028004_DB_COUNT_CONTROL, RADV_TRACKED_DB_COUNT_CONTROL, db_count_control); if (pdev->info.gfx_level >= GFX12) {
radeon_opt_set_context_reg(cmd_buffer, R_028060_DB_COUNT_CONTROL, RADV_TRACKED_DB_COUNT_CONTROL,
db_count_control);
} else {
radeon_opt_set_context_reg(cmd_buffer, R_028004_DB_COUNT_CONTROL, RADV_TRACKED_DB_COUNT_CONTROL,
db_count_control);
}
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_OCCLUSION_QUERY; cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_OCCLUSION_QUERY;
} }