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intel/eu/validate: Add some validation of ADD3

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v2: Remove spurious ALIGN_1 checks. Suggested by Matt.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23262>
This commit is contained in:
Ian Romanick
2023-05-24 19:35:40 -07:00
committed by Marge Bot
parent 1c4c76032b
commit 78dd15d8e8
2 changed files with 148 additions and 0 deletions
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41
src/intel/compiler/brw_eu_validate.c
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@@ -2279,6 +2279,47 @@ instruction_restrictions(const struct brw_isa_info *isa,
}
if (brw_inst_opcode(isa, inst) == BRW_OPCODE_ADD3) {
const enum brw_reg_type dst_type = inst_dst_type(isa, inst);
ERROR_IF(dst_type != BRW_REGISTER_TYPE_D &&
dst_type != BRW_REGISTER_TYPE_UD &&
dst_type != BRW_REGISTER_TYPE_W &&
dst_type != BRW_REGISTER_TYPE_UW,
"Destination must be integer D, UD, W, or UW type.");
for (unsigned i = 0; i < 3; i++) {
enum brw_reg_type src_type;
switch (i) {
case 0: src_type = brw_inst_3src_a1_src0_type(devinfo, inst); break;
case 1: src_type = brw_inst_3src_a1_src1_type(devinfo, inst); break;
case 2: src_type = brw_inst_3src_a1_src2_type(devinfo, inst); break;
default: unreachable("invalid src");
}
ERROR_IF(src_type != BRW_REGISTER_TYPE_D &&
src_type != BRW_REGISTER_TYPE_UD &&
src_type != BRW_REGISTER_TYPE_W &&
src_type != BRW_REGISTER_TYPE_UW,
"Source must be integer D, UD, W, or UW type.");
if (i == 0) {
if (brw_inst_3src_a1_src0_is_imm(devinfo, inst)) {
ERROR_IF(src_type != BRW_REGISTER_TYPE_W &&
src_type != BRW_REGISTER_TYPE_UW,
"Immediate source must be integer W or UW type.");
}
} else if (i == 2) {
if (brw_inst_3src_a1_src2_is_imm(devinfo, inst)) {
ERROR_IF(src_type != BRW_REGISTER_TYPE_W &&
src_type != BRW_REGISTER_TYPE_UW,
"Immediate source must be integer W or UW type.");
}
}
}
}
if (brw_inst_opcode(isa, inst) == BRW_OPCODE_OR ||
brw_inst_opcode(isa, inst) == BRW_OPCODE_AND ||
brw_inst_opcode(isa, inst) == BRW_OPCODE_XOR ||