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gallium/radeon: add micro_tile_mode to radeon_surf

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2016-06-08 20:24:21 +02:00
parent 63c5d5c6c4
commit 789618e3b4
3 changed files with 43 additions and 3 deletions
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1
src/gallium/drivers/radeon/radeon_winsys.h
View File

@@ -398,6 +398,7 @@ struct radeon_surf {
uint32_t pipe_config;
uint32_t num_banks;
uint32_t macro_tile_index;
uint32_t micro_tile_mode; /* displayable, thin, depth, rotated */
uint64_t dcc_size;
uint64_t dcc_alignment;

15
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
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@@ -255,6 +255,20 @@ static int compute_level(struct amdgpu_winsys *ws,
return 0;
}
#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
static void set_micro_tile_mode(struct radeon_surf *surf,
struct radeon_info *info)
{
uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
}
static int amdgpu_surface_init(struct radeon_winsys *rws,
struct radeon_surf *surf)
{
@@ -411,6 +425,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (level == 0) {
surf->bo_alignment = AddrSurfInfoOut.baseAlign;
surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
set_micro_tile_mode(surf, &ws->info);
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {

30
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
View File

@@ -45,6 +45,27 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
return index;
}
#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
static void set_micro_tile_mode(struct radeon_surf *surf,
struct radeon_info *info)
{
uint32_t tile_mode;
if (info->chip_class < SI) {
surf->micro_tile_mode = 0;
return;
}
tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
}
static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
const struct radeon_surf_level *level_ws)
{
@@ -114,7 +135,8 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
}
}
static void surf_drm_to_winsys(struct radeon_surf *surf_ws,
static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
struct radeon_surf *surf_ws,
const struct radeon_surface *surf_drm)
{
int i;
@@ -153,6 +175,8 @@ static void surf_drm_to_winsys(struct radeon_surf *surf_ws,
surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
}
set_micro_tile_mode(surf_ws, &ws->info);
}
static int radeon_winsys_surface_init(struct radeon_winsys *rws,
@@ -168,7 +192,7 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
if (r)
return r;
surf_drm_to_winsys(surf_ws, &surf_drm);
surf_drm_to_winsys(ws, surf_ws, &surf_drm);
return 0;
}
@@ -185,7 +209,7 @@ static int radeon_winsys_surface_best(struct radeon_winsys *rws,
if (r)
return r;
surf_drm_to_winsys(surf_ws, &surf_drm);
surf_drm_to_winsys(ws, surf_ws, &surf_drm);
return 0;
}