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radeonsi: fix typos

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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22432>
This commit is contained in:
Harri Nieminen
2023-04-11 23:37:34 +03:00
committed by Marge Bot
parent 701b6520f5
commit 7851b6fd48
16 changed files with 29 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
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@@ -108,7 +108,7 @@ bool gfx10_ngg_calculate_subgroup_info(struct si_shader *shader)
/* All these are in dwords. The maximum is 16K dwords (64KB) of LDS per workgroup. */
const unsigned scratch_lds_size = gfx10_ngg_get_scratch_dw_size(shader);
/* Scrach is at last of LDS space and 2 dwords aligned, so it may cost more for alignment. */
/* Scratch is at last of LDS space and 2 dwords aligned, so it may cost more for alignment. */
const unsigned max_lds_size = 16 * 1024 - ALIGN(scratch_lds_size, 2);
const unsigned target_lds_size = max_lds_size;
unsigned esvert_lds_size = 0;

4
src/gallium/drivers/radeonsi/radeon_uvd.c
View File

@@ -401,7 +401,7 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
}
} else {
// the firmware seems to allways assume a minimum of ref frames
// the firmware seems to always assume a minimum of ref frames
max_references = MAX2(NUM_H264_REFS, max_references);
// reference picture buffer
dpb_size = image_size * max_references;
@@ -433,7 +433,7 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
break;
case PIPE_VIDEO_FORMAT_VC1:
// the firmware seems to allways assume a minimum of ref frames
// the firmware seems to always assume a minimum of ref frames
max_references = MAX2(NUM_VC1_REFS, max_references);
// reference picture buffer

20
src/gallium/drivers/radeonsi/radeon_vcn_av1_default.h
View File

@@ -143,7 +143,7 @@ typedef enum {
#define DRL_MODE_CONTEXTS 3
#define INTER_COMPOUND_MODES (1 + AV1_NEW_NEWMV - AV1_NEAREST_NEARESTMV)
#define PALATTE_BSIZE_CTXS 9
#define PALETTE_BSIZE_CTXS 9
#define PALETTE_COLOR_INDEX_CONTEXTS 5
#define PALETTE_Y_MODE_CONTEXTS 3
#define PALETTE_UV_MODE_CONTEXTS 2
@@ -440,7 +440,7 @@ typedef struct rvcn_av1_vcn4_frame_contexts {
uint16_t skip_mode_cdfs[SKIP_CONTEXTS][CDF_SIZE(2)];
uint16_t skip_cdfs[SKIP_CONTEXTS][CDF_SIZE(2)];
uint16_t intra_inter_cdf[AV1_INTRA_INTER_CONTEXTS][CDF_SIZE(2)];
uint16_t palette_y_mode_cdf[PALATTE_BSIZE_CTXS][PALETTE_Y_MODE_CONTEXTS][CDF_SIZE(2)];
uint16_t palette_y_mode_cdf[PALETTE_BSIZE_CTXS][PALETTE_Y_MODE_CONTEXTS][CDF_SIZE(2)];
uint16_t palette_uv_mode_cdf[PALETTE_UV_MODE_CONTEXTS][CDF_SIZE(2)];
uint16_t filter_intra_cdfs[AV1_BLOCK_SIZES_ALL][CDF_SIZE(2)];
uint16_t wiener_restore_cdf[CDF_SIZE(2)];
@@ -497,8 +497,8 @@ typedef struct rvcn_av1_vcn4_frame_contexts {
uint16_t filter_intra_mode_cdf[CDF_SIZE(FILTER_INTRA_MODES)];
uint16_t eob_flag_cdf32[AV1_PLANE_TYPES][2][CDF_SIZE(6)];
uint16_t eob_flag_cdf64[AV1_PLANE_TYPES][2][CDF_SIZE(7)];
uint16_t palette_y_size_cdf[PALATTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)];
uint16_t palette_uv_size_cdf[PALATTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)];
uint16_t palette_y_size_cdf[PALETTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)];
uint16_t palette_uv_size_cdf[PALETTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)];
uint16_t angle_delta_cdf[DIRECTIONAL_MODES][CDF_SIZE(2 * MAX_ANGLE_DELTA + 1)];
uint16_t reserve3[6];
uint16_t eob_flag_cdf128[AV1_PLANE_TYPES][2][CDF_SIZE(8)];
@@ -2488,7 +2488,7 @@ static const uint16_t default_comp_bwdref_cdf[AV1_REF_CONTEXTS][BWD_REFS - 1][CD
{ { AOM_CDF2(2235) },{ AOM_CDF2(1423) } }, { { AOM_CDF2(17182) },{ AOM_CDF2(15175) } }, { { AOM_CDF2(30606) },{ AOM_CDF2(30489) } }
};
static const uint16_t default_palette_y_size_cdf[PALATTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)] =
static const uint16_t default_palette_y_size_cdf[PALETTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)] =
{
{ AOM_CDF7(7952, 13000, 18149, 21478, 25527, 29241) }, { AOM_CDF7(7139, 11421, 16195, 19544, 23666, 28073) },
{ AOM_CDF7(7788, 12741, 17325, 20500, 24315, 28530) }, { AOM_CDF7(8271, 14064, 18246, 21564, 25071, 28533) },
@@ -2496,7 +2496,7 @@ static const uint16_t default_palette_y_size_cdf[PALATTE_BSIZE_CTXS][CDF_SIZE(PA
{ AOM_CDF7(14940, 20797, 21678, 24186, 27033, 28999) }
};
static const uint16_t default_palette_uv_size_cdf[PALATTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)] =
static const uint16_t default_palette_uv_size_cdf[PALETTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)] =
{
{ AOM_CDF7(8713, 19979, 27128, 29609, 31331, 32272) }, { AOM_CDF7(5839, 15573, 23581, 26947, 29848, 31700) },
{ AOM_CDF7(4426, 11260, 17999, 21483, 25863, 29430) }, { AOM_CDF7(3228, 9464, 14993, 18089, 22523, 27420) },
@@ -2504,7 +2504,7 @@ static const uint16_t default_palette_uv_size_cdf[PALATTE_BSIZE_CTXS][CDF_SIZE(P
{ AOM_CDF7(1269, 5435, 10433, 18963, 21700, 25865) }
};
static const uint16_t default_palette_y_mode_cdf[PALATTE_BSIZE_CTXS][PALETTE_Y_MODE_CONTEXTS][CDF_SIZE(2)] =
static const uint16_t default_palette_y_mode_cdf[PALETTE_BSIZE_CTXS][PALETTE_Y_MODE_CONTEXTS][CDF_SIZE(2)] =
{
{ { AOM_CDF2(31676) },{ AOM_CDF2(3419) },{ AOM_CDF2(1261) } }, { { AOM_CDF2(31912) },{ AOM_CDF2(2859) },{ AOM_CDF2(980) } },
{ { AOM_CDF2(31823) },{ AOM_CDF2(3400) },{ AOM_CDF2(781) } }, { { AOM_CDF2(32030) },{ AOM_CDF2(3561) },{ AOM_CDF2(904) } },
@@ -2706,7 +2706,7 @@ typedef struct rvcn_av1_frame_context_s
uint16_t skip_mode_cdfs[SKIP_CONTEXTS][CDF_SIZE(2)];
uint16_t skip_cdfs[SKIP_CONTEXTS][CDF_SIZE(2)];
uint16_t intra_inter_cdf[AV1_INTRA_INTER_CONTEXTS][CDF_SIZE(2)];
uint16_t palette_y_mode_cdf[PALATTE_BSIZE_CTXS][PALETTE_Y_MODE_CONTEXTS][CDF_SIZE(2)];
uint16_t palette_y_mode_cdf[PALETTE_BSIZE_CTXS][PALETTE_Y_MODE_CONTEXTS][CDF_SIZE(2)];
uint16_t palette_uv_mode_cdf[PALETTE_UV_MODE_CONTEXTS][CDF_SIZE(2)];
uint16_t filter_intra_cdfs[AV1_BLOCK_SIZES_ALL][CDF_SIZE(2)];
uint16_t wiener_restore_cdf[CDF_SIZE(2)];
@@ -2763,8 +2763,8 @@ typedef struct rvcn_av1_frame_context_s
uint16_t filter_intra_mode_cdf[CDF_SIZE(FILTER_INTRA_MODES)];
uint16_t eob_flag_cdf32[AV1_PLANE_TYPES][2][CDF_SIZE(6)];
uint16_t eob_flag_cdf64[AV1_PLANE_TYPES][2][CDF_SIZE(7)];
uint16_t palette_y_size_cdf[PALATTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)];
uint16_t palette_uv_size_cdf[PALATTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)];
uint16_t palette_y_size_cdf[PALETTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)];
uint16_t palette_uv_size_cdf[PALETTE_BSIZE_CTXS][CDF_SIZE(PALETTE_SIZES)];
uint16_t angle_delta_cdf[DIRECTIONAL_MODES][CDF_SIZE(2 * MAX_ANGLE_DELTA + 1)];
uint16_t reserve3[6];
uint16_t eob_flag_cdf128[AV1_PLANE_TYPES][2][CDF_SIZE(8)];

2
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
View File

@@ -2690,7 +2690,7 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
break;
case PIPE_VIDEO_FORMAT_VC1:
// the firmware seems to allways assume a minimum of ref frames
// the firmware seems to always assume a minimum of ref frames
max_references = MAX2(NUM_VC1_REFS, max_references);
// reference picture buffer

2
src/gallium/drivers/radeonsi/radeon_vcn_enc.h
View File

@@ -116,7 +116,7 @@
#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0
#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1
#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2
#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE_ACROSS_SLICE_BOUNDARY 2
#define RENCODE_INTRA_REFRESH_MODE_NONE 0
#define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1

2
src/gallium/drivers/radeonsi/si_blit.c
View File

@@ -520,7 +520,7 @@ static void si_blit_decompress_color(struct si_context *sctx, struct si_texture
custom_blend == sctx->custom_blend_dcc_decompress)
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
/* When running FMASK decompresion with DCC, we need to run the "eliminate fast clear" pass
/* When running FMASK decompression with DCC, we need to run the "eliminate fast clear" pass
* separately because FMASK decompression doesn't eliminate DCC fast clear. This makes
* render->texture transitions more expensive. It can be disabled by
* allow_dcc_msaa_clear_to_reg_for_bpp.

2
src/gallium/drivers/radeonsi/si_buffer.c
View File

@@ -309,7 +309,7 @@ static void si_invalidate_resource(struct pipe_context *ctx, struct pipe_resourc
struct si_context *sctx = (struct si_context *)ctx;
struct si_resource *buf = si_resource(resource);
/* We currently only do anyting here for buffers */
/* We currently only do anything here for buffers */
if (resource->target == PIPE_BUFFER)
(void)si_invalidate_buffer(sctx, buf);
}

2
src/gallium/drivers/radeonsi/si_compute_blit.c
View File

@@ -494,7 +494,7 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
sctx->b.buffer_subdata(&sctx->b, dst,
PIPE_MAP_WRITE |
/* TC forbids drivers to invalidate buffers and infer unsychronized mappings,
/* TC forbids drivers to invalidate buffers and infer unsynchronized mappings,
* so suppress those optimizations. */
(sctx->tc ? TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED |
TC_TRANSFER_MAP_NO_INVALIDATE : 0),

2
src/gallium/drivers/radeonsi/si_debug.c
View File

@@ -536,7 +536,7 @@ static void si_dump_bo_list(struct si_context *sctx, const struct radeon_saved_c
if (!saved->bo_list)
return;
/* Sort the list according to VM adddresses first. */
/* Sort the list according to VM addresses first. */
qsort(saved->bo_list, saved->bo_count, sizeof(saved->bo_list[0]), (void *)bo_list_compare_va);
fprintf(f, "Buffer list (in units of pages = 4kB):\n" COLOR_YELLOW

2
src/gallium/drivers/radeonsi/si_get.c
View File

@@ -34,7 +34,7 @@
#include "vl/vl_video_buffer.h"
#include <sys/utsname.h>
/* The capabilties reported by the kernel has priority
/* The capabilities reported by the kernel has priority
over the existing logic in si_get_video_param */
#define QUERYABLE_KERNEL (!!(sscreen->info.drm_minor >= 41))
#define KERNEL_DEC_CAP(codec, attrib) \

2
src/gallium/drivers/radeonsi/si_pipe.c
View File

@@ -1397,7 +1397,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
* z = [2..8]
* c = [2..8]
*
* Only MSAA color and depth buffers are overriden.
* Only MSAA color and depth buffers are overridden.
*/
if (sscreen->info.has_eqaa_surface_allocator) {
const char *eqaa = debug_get_option("EQAA", NULL);

2
src/gallium/drivers/radeonsi/si_shader_llvm_ps.c
View File

@@ -481,7 +481,7 @@ static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
* - polygon stippling
*
* All preloaded SGPRs and VGPRs are passed through unmodified unless they are
* overriden by other states. (e.g. per-sample interpolation)
* overridden by other states. (e.g. per-sample interpolation)
* Interpolated colors are stored after the preloaded VGPRs.
*/
void si_llvm_build_ps_prolog(struct si_shader_context *ctx, union si_shader_part_key *key,

4
src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
View File

@@ -577,8 +577,8 @@ void si_llvm_ls_build_end(struct si_shader_context *ctx)
}
/**
* Compile the TCS epilog function. This writes tesselation factors to memory
* based on the output primitive type of the tesselator (determined by TES).
* Compile the TCS epilog function. This writes tessellation factors to memory
* based on the output primitive type of the tessellator (determined by TES).
*/
void si_llvm_build_tcs_epilog(struct si_shader_context *ctx, union si_shader_part_key *key,
UNUSED bool separate_epilog)

2
src/gallium/drivers/radeonsi/si_state.c
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@@ -5962,7 +5962,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
S_028B50_ACCUM_QUAD(11) |
S_028B50_DONUT_SPLIT_GFX81(16);
/* Testing with Unigine Heaven extreme tesselation yielded best results
/* Testing with Unigine Heaven extreme tessellation yielded best results
* with TRAP_SPLIT = 3.
*/
if (sctx->family == CHIP_FIJI || sctx->family >= CHIP_POLARIS10)

4
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View File

@@ -1868,7 +1868,7 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
shader->ps.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
/* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
* Possible vaules:
* Possible values:
* 0 -> Position = pixel center
* 1 -> Position = pixel centroid
* 2 -> Position = at sample position
@@ -3167,7 +3167,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
if (util_rast_prim_is_triangles(sel->rast_prim))
sel->rast_prim = PIPE_PRIM_TRIANGLES;
/* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation so
/* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tessellation so
* we can't split workgroups. Disable ngg if any of the following conditions is true:
* - num_invocations * gs.vertices_out > 256
* - LDS usage is too high

4
src/gallium/drivers/radeonsi/si_texture.c
View File

@@ -1255,7 +1255,7 @@ si_texture_create_with_modifier(struct pipe_screen *screen,
if (templ->nr_samples >= 2) {
/* This is hackish (overwriting the const pipe_resource template),
* but should be harmless and gallium frontends can also see
* the overriden number of samples in the created pipe_resource.
* the overridden number of samples in the created pipe_resource.
*/
if (is_zs && sscreen->eqaa_force_z_samples) {
((struct pipe_resource *)templ)->nr_samples =
@@ -2358,7 +2358,7 @@ static int si_get_sparse_texture_virtual_page_size(struct pipe_screen *screen,
if (multi_sample && sscreen->info.gfx_level != GFX9)
return 0;
/* Unsupport formats. */
/* Unsupported formats. */
/* TODO: support these formats. */
if (util_format_is_depth_or_stencil(format) ||
util_format_get_num_planes(format) > 1 ||