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radv: configure VGT_VERTEX_REUSE at pipeline creation

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2017-10-06 09:53:21 +02:00
parent b09b43b166
commit 7824cb4b03
3 changed files with 16 additions and 10 deletions
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18
src/amd/vulkan/radv_cmd_buffer.c
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@@ -923,19 +923,17 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
} }
} }
static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer, static void
struct radv_pipeline *pipeline) radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline)
{ {
uint32_t vtx_reuse_depth = 30; struct radeon_winsys_cs *cs = cmd_buffer->cs;
if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10) if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
return; return;
if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) { radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) pipeline->graphics.vtx_reuse_depth);
vtx_reuse_depth = 14;
}
radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
vtx_reuse_depth);
} }
static void static void
@@ -954,7 +952,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
radv_emit_tess_shaders(cmd_buffer, pipeline); radv_emit_tess_shaders(cmd_buffer, pipeline);
radv_emit_geometry_shader(cmd_buffer, pipeline); radv_emit_geometry_shader(cmd_buffer, pipeline);
radv_emit_fragment_shader(cmd_buffer, pipeline); radv_emit_fragment_shader(cmd_buffer, pipeline);
polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline); radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
cmd_buffer->scratch_size_needed = cmd_buffer->scratch_size_needed =
MAX2(cmd_buffer->scratch_size_needed, MAX2(cmd_buffer->scratch_size_needed,

7
src/amd/vulkan/radv_pipeline.c
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@@ -2087,6 +2087,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
else else
pipeline->graphics.vtx_emit_num = 2; pipeline->graphics.vtx_emit_num = 2;
} }
pipeline->graphics.vtx_reuse_depth = 30;
if (radv_pipeline_has_tess(pipeline) &&
pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
pipeline->graphics.vtx_reuse_depth = 14;
}
if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) { if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
radv_dump_pipeline_stats(device, pipeline); radv_dump_pipeline_stats(device, pipeline);
} }

1
src/amd/vulkan/radv_private.h
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@@ -1095,6 +1095,7 @@ struct radv_pipeline {
bool ia_switch_on_eoi; bool ia_switch_on_eoi;
bool partial_vs_wave; bool partial_vs_wave;
uint8_t vtx_emit_num; uint8_t vtx_emit_num;
uint32_t vtx_reuse_depth;
struct radv_prim_vertex_count prim_vertex_count; struct radv_prim_vertex_count prim_vertex_count;
bool can_use_guardband; bool can_use_guardband;
} graphics; } graphics;