From 77ecf9149c7fdadbb24b471785c4d5b4e285f2df Mon Sep 17 00:00:00 2001 From: Sviatoslav Peleshko Date: Wed, 30 Nov 2022 07:05:51 +0200 Subject: [PATCH] anv: Defer flushing PIPE_CONTROL bits forbidden in CCS while in GPGPU mode Fixes: 313aeee8 ("anv: Use pending pipe control mechanism in flush_pipeline_select() ") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7816 Signed-off-by: Sviatoslav Peleshko Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/vulkan/anv_private.h | 18 +++++++++++++ src/intel/vulkan/genX_cmd_buffer.c | 43 ++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index c24eb89cc7d..82e42cbc8f4 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2123,6 +2123,24 @@ enum anv_pipe_bits { ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \ ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) +/* PIPE_CONTROL bits that should be set only in 3D RCS mode. + * For more details see genX(emit_apply_pipe_flushes). + */ +#define ANV_PIPE_GFX_BITS ( \ + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \ + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \ + ANV_PIPE_TILE_CACHE_FLUSH_BIT | \ + ANV_PIPE_DEPTH_STALL_BIT | \ + ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \ + (GFX_VERx10 >= 125 ? ANV_PIPE_PSS_STALL_SYNC_BIT : 0) | \ + ANV_PIPE_VF_CACHE_INVALIDATE_BIT) + +/* PIPE_CONTROL bits that should be set only in Media/GPGPU RCS mode. + * For more details see genX(emit_apply_pipe_flushes). + */ +#define ANV_PIPE_GPGPU_BITS ( \ + (GFX_VERx10 >= 125 ? ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT : 0)) + enum intel_ds_stall_flag anv_pipe_flush_bit_to_ds_stall_flag(enum anv_pipe_bits bits); diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index d04b4b5c81e..f717d976476 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1808,6 +1808,45 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, uint32_t current_pipeline, enum anv_pipe_bits bits) { +#if GFX_VER >= 12 + /* From the TGL PRM, Volume 2a, "PIPE_CONTROL": + * + * "SW must follow below programming restrictions when programming + * PIPE_CONTROL command [for ComputeCS]: + * ... + * Following bits must not be set when programmed for ComputeCS: + * - "Render Target Cache Flush Enable", "Depth Cache Flush Enable" + * and "Tile Cache Flush Enable" + * - "Depth Stall Enable", Stall at Pixel Scoreboard and + * "PSD Sync Enable". + * - "OVR Tile 0 Flush", "TBIMR Force Batch Closure", + * "AMFS Flush Enable", "VF Cache Invalidation Enable" and + * "Global Snapshot Count Reset"." + * + * XXX: According to spec this should not be a concern for a regular + * RCS in GPGPU mode, but during testing it was found that at least + * "VF Cache Invalidation Enable" bit is ignored in such case. + * This can cause us to miss some important invalidations + * (e.g. from CmdPipelineBarriers) and have incoherent data. + * + * There is also a Wa_1606932921 "RCS is not waking up fixed function clock + * when specific 3d related bits are programmed in pipecontrol in + * compute mode" that suggests us not to use "RT Cache Flush" in GPGPU mode. + * + * The other bits are not confirmed to cause problems, but included here + * just to be safe, as they're also not really relevant in the GPGPU mode, + * and having them doesn't seem to cause any regressions. + * + * So if we're currently in GPGPU mode, we hide some bits from + * this flush, and will flush them only when we'll be able to. + * Similar thing with GPGPU-only bits. + */ + enum anv_pipe_bits defer_bits = bits & + (current_pipeline == GPGPU ? ANV_PIPE_GFX_BITS: ANV_PIPE_GPGPU_BITS); + + bits &= ~defer_bits; +#endif + /* * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization": * @@ -2071,6 +2110,10 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, bits &= ~ANV_PIPE_INVALIDATE_BITS; } +#if GFX_VER >= 12 + bits |= defer_bits; +#endif + return bits; }