radv: add an option to configure the trap handler exceptions
This introduces RADV_TRAP_HANDLER_EXCP to configure the various shader exceptions. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31902>
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@@ -1492,6 +1492,20 @@ RADV driver environment variables
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enable/disable the experimental trap handler for debugging GPU hangs on GFX8
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enable/disable the experimental trap handler for debugging GPU hangs on GFX8
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(disabled by default)
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(disabled by default)
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.. envvar:: RADV_TRAP_HANDLER_EXCP
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a comma-separated list of named flags to configure the trap handler
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exceptions, see the list below:
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``mem_viol``
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enable memory violation exception
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``float_div_by_zero``
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enable floating point division by zero exception
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``float_overflow``
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enable floating point overflow exception
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``float_underflow``
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enable floating point underflow exception
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.. envvar:: RADV_RRA_TRACE_VALIDATE
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.. envvar:: RADV_RRA_TRACE_VALIDATE
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enable validation of captured acceleration structures. Can be
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enable validation of captured acceleration structures. Can be
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@@ -81,6 +81,13 @@ enum {
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RADV_PERFTEST_VIDEO_ENCODE = 1u << 16,
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RADV_PERFTEST_VIDEO_ENCODE = 1u << 16,
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};
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};
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enum {
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RADV_TRAP_EXCP_MEM_VIOL = 1u << 0,
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RADV_TRAP_EXCP_FLOAT_DIV_BY_ZERO = 1u << 1,
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RADV_TRAP_EXCP_FLOAT_OVERFLOW = 1u << 2,
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RADV_TRAP_EXCP_FLOAT_UNDERFLOW = 1u << 3,
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};
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bool radv_init_trace(struct radv_device *device);
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bool radv_init_trace(struct radv_device *device);
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void radv_finish_trace(struct radv_device *device);
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void radv_finish_trace(struct radv_device *device);
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@@ -100,6 +100,14 @@ static const struct debug_control radv_perftest_options[] = {{"localbos", RADV_P
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{"video_encode", RADV_PERFTEST_VIDEO_ENCODE},
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{"video_encode", RADV_PERFTEST_VIDEO_ENCODE},
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{NULL, 0}};
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{NULL, 0}};
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static const struct debug_control radv_trap_excp_options[] = {
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{"mem_viol", RADV_PERFTEST_LOCAL_BOS},
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{"float_div_by_zero", RADV_PERFTEST_DCC_MSAA},
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{"float_overflow", RADV_PERFTEST_BO_LIST},
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{"float_underflow", RADV_PERFTEST_CS_WAVE_32},
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{NULL, 0},
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};
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const char *
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const char *
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radv_get_perftest_option_name(int id)
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radv_get_perftest_option_name(int id)
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{
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{
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@@ -343,6 +351,7 @@ radv_CreateInstance(const VkInstanceCreateInfo *pCreateInfo, const VkAllocationC
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instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"), radv_debug_options);
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instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"), radv_debug_options);
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instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"), radv_perftest_options);
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instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"), radv_perftest_options);
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instance->trap_excp_flags = parse_debug_string(getenv("RADV_TRAP_HANDLER_EXCP"), radv_trap_excp_options);
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instance->profile_pstate = radv_parse_pstate(debug_get_option("RADV_PROFILE_PSTATE", "peak"));
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instance->profile_pstate = radv_parse_pstate(debug_get_option("RADV_PROFILE_PSTATE", "peak"));
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/* When RADV_FORCE_FAMILY is set, the driver creates a null
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/* When RADV_FORCE_FAMILY is set, the driver creates a null
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@@ -42,6 +42,7 @@ struct radv_instance {
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uint64_t debug_flags;
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uint64_t debug_flags;
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uint64_t perftest_flags;
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uint64_t perftest_flags;
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uint64_t trap_excp_flags;
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enum radeon_ctx_pstate profile_pstate;
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enum radeon_ctx_pstate profile_pstate;
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struct {
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struct {
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@@ -1889,6 +1889,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
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const struct radv_shader_args *args)
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const struct radv_shader_args *args)
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{
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct radv_instance *instance = radv_physical_device_instance(pdev);
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struct ac_shader_config *config = &binary->config;
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struct ac_shader_config *config = &binary->config;
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if (binary->type == RADV_BINARY_TYPE_RTLD) {
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if (binary->type == RADV_BINARY_TYPE_RTLD) {
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@@ -1940,6 +1941,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
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(pdev->info.gfx_level < GFX10 && num_shared_vgprs == 0));
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(pdev->info.gfx_level < GFX10 && num_shared_vgprs == 0));
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unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
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unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
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unsigned excp_en = 0, excp_en_msb = 0;
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unsigned excp_en = 0, excp_en_msb = 0;
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bool dx10_clamp = pdev->info.gfx_level < GFX12;
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config->num_vgprs = num_vgprs;
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config->num_vgprs = num_vgprs;
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config->num_sgprs = num_sgprs;
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config->num_sgprs = num_sgprs;
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@@ -1949,11 +1951,24 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
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S_00B12C_TRAP_PRESENT(trap_enabled);
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S_00B12C_TRAP_PRESENT(trap_enabled);
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if (trap_enabled) {
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if (trap_enabled) {
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/* Configure the shader exceptions like memory violation, etc.
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/* Configure the shader exceptions like memory violation, etc. */
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* TODO: Enable (and validate) more exceptions.
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if (instance->trap_excp_flags & RADV_TRAP_EXCP_MEM_VIOL) {
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*/
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excp_en |= 1 << 8; /* for the graphics stages */
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excp_en = 1 << 8; /* mem_viol for the graphics stages */
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excp_en_msb |= 1 << 1; /* for the compute stage */
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excp_en_msb = 1 << 1; /* mem_viol for the compute stage */
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}
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if (instance->trap_excp_flags & RADV_TRAP_EXCP_FLOAT_DIV_BY_ZERO)
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excp_en |= 1 << 2;
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if (instance->trap_excp_flags & RADV_TRAP_EXCP_FLOAT_OVERFLOW)
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excp_en |= 1 << 3;
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if (instance->trap_excp_flags & RADV_TRAP_EXCP_FLOAT_UNDERFLOW)
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excp_en |= 1 << 4;
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if (instance->trap_excp_flags &
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(RADV_TRAP_EXCP_FLOAT_DIV_BY_ZERO | RADV_TRAP_EXCP_FLOAT_OVERFLOW | RADV_TRAP_EXCP_FLOAT_UNDERFLOW)) {
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/* It seems needed to disable DX10_CLAMP, otherwise the float exceptions aren't thrown. */
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dx10_clamp = false;
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}
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}
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}
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if (!pdev->use_ngg_streamout) {
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if (!pdev->use_ngg_streamout) {
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@@ -1962,8 +1977,8 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
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S_00B12C_SO_EN(!!info->so.num_outputs);
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S_00B12C_SO_EN(!!info->so.num_outputs);
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}
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}
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config->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / (info->wave_size == 32 ? 8 : 4)) |
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config->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / (info->wave_size == 32 ? 8 : 4)) | S_00B848_DX10_CLAMP(dx10_clamp) |
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S_00B848_DX10_CLAMP(pdev->info.gfx_level < GFX12) | S_00B848_FLOAT_MODE(config->float_mode);
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S_00B848_FLOAT_MODE(config->float_mode);
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if (pdev->info.gfx_level >= GFX10) {
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if (pdev->info.gfx_level >= GFX10) {
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config->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(args->num_user_sgprs >> 5);
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config->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(args->num_user_sgprs >> 5);
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