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anv: remove some gen8 specifics handled now in hasvk

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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20342>
This commit is contained in:
Tapani Pälli
2022-12-15 20:28:21 +02:00
parent 09d5c55836
commit 77244e30b6
5 changed files with 5 additions and 64 deletions
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8
src/intel/vulkan/anv_batch_chain.c
View File

@@ -433,17 +433,11 @@ emit_batch_buffer_start(struct anv_cmd_buffer *cmd_buffer,
* gens.
*/
#define GFX7_MI_BATCH_BUFFER_START_length 2
#define GFX7_MI_BATCH_BUFFER_START_length_bias 2
const uint32_t gfx7_length =
GFX7_MI_BATCH_BUFFER_START_length - GFX7_MI_BATCH_BUFFER_START_length_bias;
const uint32_t gfx8_length =
GFX8_MI_BATCH_BUFFER_START_length - GFX8_MI_BATCH_BUFFER_START_length_bias;
anv_batch_emit(&cmd_buffer->batch, GFX8_MI_BATCH_BUFFER_START, bbs) {
bbs.DWordLength = cmd_buffer->device->info->ver < 8 ?
gfx7_length : gfx8_length;
bbs.DWordLength = gfx8_length;
bbs.SecondLevelBatchBuffer = Firstlevelbatch;
bbs.AddressSpaceIndicator = ASI_PPGTT;
bbs.BatchBufferStartAddress = (struct anv_address) { bo, offset };

2
src/intel/vulkan/anv_device.c
View File

@@ -2092,7 +2092,7 @@ anv_get_physical_device_properties_1_2(struct anv_physical_device *pdevice,
* Restriction : Half-float denorms are always retained."
*/
p->shaderDenormFlushToZeroFloat16 = false;
p->shaderDenormPreserveFloat16 = pdevice->info.ver > 8;
p->shaderDenormPreserveFloat16 = true;
p->shaderRoundingModeRTEFloat16 = true;
p->shaderRoundingModeRTZFloat16 = true;
p->shaderSignedZeroInfNanPreserveFloat16 = true;

33
src/intel/vulkan/anv_image.c
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@@ -372,27 +372,6 @@ can_fast_clear_with_non_zero_color(const struct intel_device_info *devinfo,
if (!isl_formats_have_same_bits_per_channel(img_format, view_format))
return false;
/* Switching between any of those format types on Gfx7/8 will cause
* problems https://gitlab.freedesktop.org/mesa/mesa/-/issues/1711
*/
if (devinfo->ver <= 8) {
if (isl_format_has_float_channel(img_format) &&
!isl_format_has_float_channel(view_format))
return false;
if (isl_format_has_int_channel(img_format) &&
!isl_format_has_int_channel(view_format))
return false;
if (isl_format_has_unorm_channel(img_format) &&
!isl_format_has_unorm_channel(view_format))
return false;
if (isl_format_has_snorm_channel(img_format) &&
!isl_format_has_snorm_channel(view_format))
return false;
}
}
return true;
@@ -695,12 +674,6 @@ add_aux_surface_if_supported(struct anv_device *device,
return VK_SUCCESS;
}
if (device->info->ver == 8 && image->vk.samples > 1) {
anv_perf_warn(VK_LOG_OBJS(&image->vk.base),
"Enable gfx8 multisampled HiZ");
return VK_SUCCESS;
}
if (INTEL_DEBUG(DEBUG_NO_HIZ))
return VK_SUCCESS;
@@ -2463,12 +2436,6 @@ anv_image_fill_surface_state(struct anv_device *device,
&offset_B, &tile_x_sa, &tile_y_sa);
assert(ok);
isl_surf = &tmp_surf;
if (device->info->ver <= 8) {
assert(surface->isl.tiling == ISL_TILING_LINEAR);
assert(tile_x_sa == 0);
assert(tile_y_sa == 0);
}
}
state_inout->address = anv_address_add(address, offset_B);

8
src/intel/vulkan/anv_private.h
View File

@@ -3678,13 +3678,7 @@ anv_can_sample_with_hiz(const struct intel_device_info * const devinfo,
if (image->vk.image_type == VK_IMAGE_TYPE_3D)
return false;
/* Allow this feature on BDW even though it is disabled in the BDW devinfo
* struct. There's documentation which suggests that this feature actually
* reduces performance on BDW, but it has only been observed to help so
* far. Sampling fast-cleared blocks on BDW must also be handled with care
* (see depth_stencil_attachment_compute_aux_usage() for more info).
*/
if (devinfo->ver != 8 && !devinfo->has_sample_with_hiz)
if (!devinfo->has_sample_with_hiz)
return false;
return image->vk.samples == 1;

18
src/intel/vulkan/genX_query.c
View File

@@ -537,15 +537,9 @@ VkResult genX(GetQueryPoolResults)(
uint64_t *slot = query_slot(pool, firstQuery + i);
uint32_t statistics = pool->pipeline_statistics;
while (statistics) {
uint32_t stat = u_bit_scan(&statistics);
UNUSED uint32_t stat = u_bit_scan(&statistics);
if (write_results) {
uint64_t result = slot[idx * 2 + 2] - slot[idx * 2 + 1];
/* WaDividePSInvocationCountBy4:BDW */
if (device->info->ver == 8 &&
(1 << stat) == VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT)
result >>= 2;
cpu_write_query_result(pData, flags, idx, result);
}
idx++;
@@ -1499,17 +1493,9 @@ void genX(CmdCopyQueryPoolResults)(
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
uint32_t statistics = pool->pipeline_statistics;
while (statistics) {
uint32_t stat = u_bit_scan(&statistics);
UNUSED uint32_t stat = u_bit_scan(&statistics);
result = compute_query_result(&b, anv_address_add(query_addr,
idx * 16 + 8));
/* WaDividePSInvocationCountBy4:BDW */
if (cmd_buffer->device->info->ver == 8 &&
(1 << stat) == VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT) {
result = mi_ushr32_imm(&b, result, 2);
}
gpu_write_query_result(&b, dest_addr, flags, idx++, result);
}
assert(idx == util_bitcount(pool->pipeline_statistics));