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radeonsi: remove AMD_DEBUG=sisched option

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sisched is not maintained anymore in LLVM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4059>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4059>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
2020-03-05 11:15:57 +01:00
parent 913d2dcd23
commit 771f16cf61
13 changed files with 10 additions and 49 deletions
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2
docs/envvars.html
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@@ -712,8 +712,6 @@ Mesa EGL supports different sets of environment variables. See the
<dt><code>preoptir</code></dt>
<dd>Print the LLVM IR before initial optimizations</dd>
<h4>Shader compilation tuning flags:</h4>
<dt><code>sisched</code></dt>
<dd>Enable LLVM SI Machine Instruction Scheduler.</dd>
<dt><code>gisel</code></dt>
<dd>Enable LLVM global instruction selector.</dd>
<dt><code>w32ge</code></dt>

3
src/amd/llvm/ac_llvm_util.c
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@@ -169,10 +169,9 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
LLVMTargetRef target = ac_get_llvm_target(triple);
snprintf(features, sizeof(features),
"+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s",
"+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
family >= CHIP_NAVI10 && !(tm_options & AC_TM_WAVE32) ?
",+wavefrontsize64,-wavefrontsize32" : "",
tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",

17
src/amd/llvm/ac_llvm_util.h
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@@ -58,15 +58,14 @@ enum ac_func_attr {
enum ac_target_machine_options {
AC_TM_SUPPORTS_SPILL = (1 << 0),
AC_TM_SISCHED = (1 << 1),
AC_TM_FORCE_ENABLE_XNACK = (1 << 2),
AC_TM_FORCE_DISABLE_XNACK = (1 << 3),
AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 4),
AC_TM_CHECK_IR = (1 << 5),
AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
AC_TM_CREATE_LOW_OPT = (1 << 7),
AC_TM_NO_LOAD_STORE_OPT = (1 << 8),
AC_TM_WAVE32 = (1 << 9),
AC_TM_FORCE_ENABLE_XNACK = (1 << 1),
AC_TM_FORCE_DISABLE_XNACK = (1 << 2),
AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 3),
AC_TM_CHECK_IR = (1 << 4),
AC_TM_ENABLE_GLOBAL_ISEL = (1 << 5),
AC_TM_CREATE_LOW_OPT = (1 << 6),
AC_TM_NO_LOAD_STORE_OPT = (1 << 7),
AC_TM_WAVE32 = (1 << 8),
};
enum ac_float_mode {

1
src/gallium/drivers/radeonsi/driinfo_radeonsi.h
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@@ -1,7 +1,6 @@
// DriConf options specific to radeonsi
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_ADAPTIVE_SYNC("true")
DRI_CONF_RADEONSI_ENABLE_SISCHED("false")
DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS("false")
DRI_CONF_RADEONSI_COMMUTATIVE_BLEND_ADD("false")
DRI_CONF_RADEONSI_ZERO_ALL_VRAM_ALLOCS("false")

6
src/gallium/drivers/radeonsi/si_pipe.c
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@@ -61,7 +61,6 @@ static const struct debug_named_value debug_options[] = {
{ "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
/* Shader compiler options the shader cache should be aware of: */
{ "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
{ "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
{ "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
{ "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
@@ -141,7 +140,6 @@ void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compil
sscreen->info.chip_class <= GFX8;
enum ac_target_machine_options tm_options =
(sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
(sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
(sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
(sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
@@ -929,7 +927,7 @@ static void si_disk_cache_create(struct si_screen *sscreen)
disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
/* These flags affect shader compilation. */
#define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
#define ALL_FLAGS (DBG(GISEL))
uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
/* Add the high bits of 32-bit addresses, which affects
@@ -1029,8 +1027,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
if (driQueryOptionb(config->options,
"glsl_correct_derivatives_after_discard"))
sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
sscreen->debug_flags |= DBG(SI_SCHED);
if (sscreen->debug_flags & DBG(INFO))
ac_print_gpu_info(&sscreen->info);

1
src/gallium/drivers/radeonsi/si_pipe.h
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@@ -150,7 +150,6 @@ enum {
/* Shader compiler options the shader cache should be aware of: */
DBG_FS_CORRECT_DERIVS_AFTER_KILL,
DBG_SI_SCHED,
DBG_GISEL,
DBG_W32_GE,
DBG_W32_PS,

4
src/util/xmlpool/ca.po
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@@ -279,10 +279,6 @@ msgid ""
"(-1) CSMT is enabled on known thread-safe drivers."
msgstr ""
#: src/util/xmlpool/t_options.h:323
msgid "Use the LLVM sisched option for shader compiles"
msgstr ""
#: src/util/xmlpool/t_options.h:328
msgid ""
"Assume no Z fights (enables aggressive out-of-order rasterization to improve "

4
src/util/xmlpool/de.po
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@@ -254,10 +254,6 @@ msgid ""
"(-1) CSMT is enabled on known thread-safe drivers."
msgstr ""
#: src/util/xmlpool/t_options.h:323
msgid "Use the LLVM sisched option for shader compiles"
msgstr ""
#: src/util/xmlpool/t_options.h:328
msgid ""
"Assume no Z fights (enables aggressive out-of-order rasterization to improve "

4
src/util/xmlpool/es.po
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@@ -265,10 +265,6 @@ msgid ""
"(-1) CSMT is enabled on known thread-safe drivers."
msgstr ""
#: src/util/xmlpool/t_options.h:323
msgid "Use the LLVM sisched option for shader compiles"
msgstr ""
#: src/util/xmlpool/t_options.h:328
msgid ""
"Assume no Z fights (enables aggressive out-of-order rasterization to improve "

4
src/util/xmlpool/fr.po
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@@ -253,10 +253,6 @@ msgid ""
"(-1) CSMT is enabled on known thread-safe drivers."
msgstr ""
#: src/util/xmlpool/t_options.h:323
msgid "Use the LLVM sisched option for shader compiles"
msgstr ""
#: src/util/xmlpool/t_options.h:328
msgid ""
"Assume no Z fights (enables aggressive out-of-order rasterization to improve "

4
src/util/xmlpool/nl.po
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@@ -249,10 +249,6 @@ msgid ""
"(-1) CSMT is enabled on known thread-safe drivers."
msgstr ""
#: src/util/xmlpool/t_options.h:323
msgid "Use the LLVM sisched option for shader compiles"
msgstr ""
#: src/util/xmlpool/t_options.h:328
msgid ""
"Assume no Z fights (enables aggressive out-of-order rasterization to improve "

4
src/util/xmlpool/sv.po
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@@ -247,10 +247,6 @@ msgid ""
"(-1) CSMT is enabled on known thread-safe drivers."
msgstr ""
#: src/util/xmlpool/t_options.h:323
msgid "Use the LLVM sisched option for shader compiles"
msgstr ""
#: src/util/xmlpool/t_options.h:328
msgid ""
"Assume no Z fights (enables aggressive out-of-order rasterization to improve "

5
src/util/xmlpool/t_options.h
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@@ -373,11 +373,6 @@ DRI_CONF_OPT_END
* \brief radeonsi specific configuration options
*/
#define DRI_CONF_RADEONSI_ENABLE_SISCHED(def) \
DRI_CONF_OPT_BEGIN_B(radeonsi_enable_sisched, def) \
DRI_CONF_DESC(en,gettext("Use the LLVM sisched option for shader compiles")) \
DRI_CONF_OPT_END
#define DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS(def) \
DRI_CONF_OPT_BEGIN_B(radeonsi_assume_no_z_fights, def) \
DRI_CONF_DESC(en,gettext("Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)")) \