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radv: remove redundant assignment of tcs.tcs_vertices_out

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It's already assigned from radv_nir_shader_info_pass() and it's only
used to configure the VGT_TF_PARAM register. Otherwise, we read it
from NIR shader info during compilation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18184>
This commit is contained in:
Samuel Pitoiset
2022-08-22 15:00:50 +02:00
committed by Marge Bot
parent 762eefdbf6
commit 76f33cbf25
1 changed files with 0 additions and 1 deletions
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src/amd/vulkan/radv_pipeline.c
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@@ -3614,7 +3614,6 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages,
stages[MESA_SHADER_TESS_EVAL].info.num_tess_patches = num_patches;
stages[MESA_SHADER_GEOMETRY].info.num_tess_patches = num_patches;
stages[MESA_SHADER_VERTEX].info.num_tess_patches = num_patches;
stages[MESA_SHADER_TESS_CTRL].info.tcs.tcs_vertices_out = tess_out_patch_size;
stages[MESA_SHADER_VERTEX].info.tcs.tcs_vertices_out = tess_out_patch_size;
if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) {