radv: remove duplicate debug_flags field
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
@@ -373,7 +373,7 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
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static void
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radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
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{
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if (cmd_buffer->device->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
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if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
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enum radv_cmd_flush_bits flags;
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/* Force wait for graphics/compute engines to be idle. */
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@@ -599,7 +599,7 @@ radv_dump_enabled_options(struct radv_device *device, FILE *f)
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fprintf(f, "Enabled debug options: ");
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mask = device->debug_flags;
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mask = device->instance->debug_flags;
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while (mask) {
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int i = u_bit_scan64(&mask);
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fprintf(f, "%s, ", radv_get_debug_option_name(i));
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@@ -1154,8 +1154,6 @@ VkResult radv_CreateDevice(
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device->instance = physical_device->instance;
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device->physical_device = physical_device;
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device->debug_flags = device->instance->debug_flags;
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device->ws = physical_device->ws;
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if (pAllocator)
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device->alloc = *pAllocator;
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@@ -3151,7 +3149,7 @@ radv_initialise_color_surface(struct radv_device *device,
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}
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if (iview->image->cmask.size &&
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!(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
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!(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
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cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
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if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
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@@ -155,7 +155,7 @@ radv_init_surface(struct radv_device *device,
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(pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
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pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
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device->physical_device->rad_info.chip_class < VI ||
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create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC))
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create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC))
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surface->flags |= RADEON_SURF_DISABLE_DCC;
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if (create_info->scanout)
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surface->flags |= RADEON_SURF_SCANOUT;
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@@ -913,7 +913,7 @@ radv_image_create(VkDevice _device,
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} else {
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/* Otherwise, try to enable HTILE for depth surfaces. */
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if (radv_image_can_enable_htile(image) &&
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!(device->debug_flags & RADV_DEBUG_NO_HIZ)) {
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!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
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radv_image_alloc_htile(image);
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image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
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} else {
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@@ -683,7 +683,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
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if (!iview->image->surface.htile_size)
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return false;
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if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
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if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
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return false;
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if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
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@@ -958,7 +958,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
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if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
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return false;
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if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
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if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
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return false;
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if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
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@@ -2093,7 +2093,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
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pipeline->graphics.vtx_reuse_depth = 14;
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}
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if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
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if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
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radv_dump_pipeline_stats(device, pipeline);
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}
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@@ -2198,7 +2198,7 @@ static VkResult radv_compute_pipeline_create(
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*pPipeline = radv_pipeline_to_handle(pipeline);
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if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
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if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
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radv_dump_pipeline_stats(device, pipeline);
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}
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return VK_SUCCESS;
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@@ -60,7 +60,7 @@ radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
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/* We don't consider allocation failure fatal, we just start with a 0-sized
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* cache. */
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if (cache->hash_table == NULL ||
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(device->debug_flags & RADV_DEBUG_NO_CACHE))
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(device->instance->debug_flags & RADV_DEBUG_NO_CACHE))
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cache->table_size = 0;
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else
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memset(cache->hash_table, 0, byte_size);
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@@ -513,7 +513,6 @@ struct radv_device {
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struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
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int queue_count[RADV_MAX_QUEUE_FAMILIES];
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struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
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uint64_t debug_flags;
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bool llvm_supports_spill;
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bool has_distributed_tess;
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@@ -174,7 +174,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
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uint32_t *spirv = (uint32_t *) module->data;
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assert(module->size % 4 == 0);
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if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV)
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if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
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radv_print_spirv(spirv, module->size, stderr);
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uint32_t num_spec_entries = 0;
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@@ -263,7 +263,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
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nir_remove_dead_variables(nir, nir_var_local);
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radv_optimize_nir(nir);
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if (device->debug_flags & RADV_DEBUG_DUMP_SHADERS)
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if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)
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nir_print_shader(nir, stderr);
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return nir;
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@@ -386,7 +386,7 @@ shader_variant_create(struct radv_device *device,
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unsigned *code_size_out)
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{
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enum radeon_family chip_family = device->physical_device->rad_info.family;
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bool dump_shaders = device->debug_flags & RADV_DEBUG_DUMP_SHADERS;
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bool dump_shaders = device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS;
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enum ac_target_machine_options tm_options = 0;
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struct radv_shader_variant *variant;
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struct ac_shader_binary binary;
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@@ -458,7 +458,7 @@ radv_shader_variant_create(struct radv_device *device,
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if (key)
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options.key = *key;
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options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
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options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
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options.supports_spill = device->llvm_supports_spill;
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return shader_variant_create(device, module, shader, shader->stage,
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